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| freescale semiconductor data sheet: advance information document number: MPC5604Bc rev. 2, 3/2009 ? freescale semiconductor, inc., 2009. all rights reserved. preliminary?subject to change without notice this document contains information on a prod uct under development. freescale reserves the right to change or discontinue this product without notice. MPC5604B/c 208 mapbga 17 x 17 x 1.7 mm 144 lqfp 20 x 20 x 1.4mm 100 lqfp 14 x 14 x 1.4 mm 32-bit mcu family built on the power architecture? for automotive body electr onics applications features: ? single issue, 32-bit cpu core complex (e200z0) ? compliant with the power architecture? embedded category ? includes an instruction set enhancement allowing variable length encoding (v le) for code size footprint reduction. with the optional encoding of mixed 16-bit and 32-bit instructions, it is possible to achieve significant code size footprint reduction. ? up to 512 kbytes on-chip flash supported with the flash controller ? up to 48 kbytes on-chip sram ? memory protection unit (mpu) with 8 region descriptors and 32-byte region granularity ? interrupt controller (intc) with 148 interrupt vectors, including 16 external interrupt sources and 18 external interrupt/wakeup sources ? frequency modulated phase-locked loop (fmpll) ? crossbar switch architecture for concurrent access to peripherals, flash, or ram from multiple bus masters ? boot assist module (bam) supports internal flash programming via a serial link (can or sci) ? timer supports input/output channels providing a range of 16-bit input capture, output compare, and pulse width modulation functions (emios-lite) ? 10-bit analog-to-digital converter (adc) ? 3 serial peripheral interface (dspi) modules ? up to 4 serial communicatio n interface (linflex) modules ? up to 6 enhanced full can (flexcan) modules with configurable buffers ? 1 inter ic communication interface (i 2 c) module ? up to 123 configurable general purpose pins supporting input and output operations (package dependent) ? real time counter (rtc) with clock source from 128 khz or 16 mhz internal rc oscillator supporting autonomous wakeup with 1 ms resolution with max timeout of 2 seconds ? up to 6 periodic interrupt timers (pit) with 32-bit counter resolution ? 1 system module timer (stm) ? nexus development inte rface (ndi) per ieee-isto 5001-2003 class two plus standard ? device/board boundary scan testing supported per joint test action group (jtag) of ieee (ieee 1149.1) ? on-chip voltage regulator (vreg) for regulation of input supply for all internal levels MPC5604B/c microcontroller data sheet
MPC5604B/c microcontrolle r data sheet, rev. 2 preliminary?subject to change without notice freescale semiconductor 2 table of contents 1 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.1 introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 device blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.2 device block summary . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3 package pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4 electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.1 introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.2 parameter classification. . . . . . . . . . . . . . . . . . . . . . . . 11 4.3 nvusro register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.3.1 nvusro[pad3v5v] field description . . . . . . . . 11 4.3.2 nvusro[oscillator_margin] field description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.4 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . 12 4.5 recommended operating conditions . . . . . . . . . . . . . . 13 4.6 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . 15 4.6.1 package thermal characteristics . . . . . . . . . . . . 15 4.6.2 power considerations . . . . . . . . . . . . . . . . . . . . 16 4.7 i/o pad electrical characteristics. . . . . . . . . . . . . . . . . . 16 4.7.1 i/o pad types . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.7.2 i/o input dc characteristics . . . . . . . . . . . . . . . 17 4.7.3 i/o output dc characteristics . . . . . . . . . . . . . . 18 4.7.4 output pin transition times. . . . . . . . . . . . . . . . . 20 4.7.5 i/o pad current specification . . . . . . . . . . . . . . . 21 4.8 nrstin electrical characteristics . . . . . . . . . . . . . . . . . 23 4.9 power management electrical characteristics . . . . . . . 25 4.9.1 voltage regulator electrical characteristics . . . . 25 4.9.2 voltage monitor electrical characteristics . . . . . 27 4.10 low voltage domain power consumption . . . . . . . . . . . 28 4.11 flash memory electrical characteristics . . . . . . . . . . . .29 4.11.1 program/erase characteristics. . . . . . . . . . . . . .29 4.11.2 flash power supply dc characteristics . . . . . . .30 4.11.3 start-up/switch-off timings. . . . . . . . . . . . . . . . .31 4.12 electromagnetic compatibility (emc) characteristics . .31 4.12.1 designing hardened software to avoid noise problems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 4.12.2 electromagnetic interference (emi) . . . . . . . . . .32 4.12.3 absolute maximum ratings (electrical sensitivity) 32 4.13 fast external crystal oscill ator (4 to 16 mhz) electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 4.14 slow external crystal o scillator (32 khz) electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 4.15 fmpll electrical characteristics . . . . . . . . . . . . . . . . . .38 4.16 fast internal rc oscillator (16 mhz) electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 4.17 slow internal rc oscillator (128 khz) electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 4.18 on-chip peripherals. . . . . . . . . . . . . . . . . . . . . . . . . . . .40 4.18.1 current consumption . . . . . . . . . . . . . . . . . . . . .40 4.18.2 dspi characteristics . . . . . . . . . . . . . . . . . . . . .41 4.18.3 nexus characteristics. . . . . . . . . . . . . . . . . . . . .46 4.18.4 jtag characteristics . . . . . . . . . . . . . . . . . . . . .47 4.18.5 adc electrical characteristics . . . . . . . . . . . . . .49 5 package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 5.1 package mechanical data . . . . . . . . . . . . . . . . . . . . . . .56 6 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 7 document revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . .65 MPC5604B/c microcontrolle r data sheet, rev. 2 preliminary?subject to change without notice freescale semiconductor 3 1 general description 1.1 introduction the MPC5604B/c is a family of next generation microcontrolle rs built on the power architect ure? embedded category. this document describes the features of the fa mily and options available within the family members, and highlights important electrical and physical char acteristics of the device. the MPC5604B/c family of 32-bit microcontrollers is the latest achievement in integrated auto motive application controllers. it belongs to an expanding family of automotive-focused produc ts designed to address the next wave of body electronics applications within the vehicle. the advanced and cost-efficient host processo r core of the MPC5604B/ c automotive controller family complies with the power archit ecture embedded category and only implements the vle (variable-length encoding) apu, providing improved code de nsity. it operates at speeds of up to 64 mhz and offers high performance processing optimized for low power consumption. it capitalizes on the available development infrastructu re of current power architecture devices and is supported with software drivers, operating systems an d configuration code to assist with users implementations. MPC5604B/c microcontrolle r data sheet, rev. 2 preliminary?subject to change without notice freescale semiconductor 4 table 1. MPC5604B/c device comparison 1 1 feature set dependent on selected peripheral mu ltiplexing?table shows example implementation feature device mpc560 2bxll mpc560 2bxlq mpc560 2cxll mpc560 3bxll mpc560 3bxlq mpc560 3cxll mpc560 4bxll mpc560 4bxlq mpc560 4bxmg mpc560 4cxll cpu e200z0h execution speed 2 2 based on 105 c ambient operating temperature static - 64 mhz code flash 256 kb 256 kb 384 kb 384 kb 512 kb 512 kb data flash 64 kb (4 16 kb) ram 24kb 32kb 28kb 40kb 32kb 48 kb 48kb mpu 8-entry adc 28 ch, 10-bit 36 ch, 10-bit 28 ch, 10-bit 28 ch, 10-bit 36 ch, 10-bit 28 ch, 10-bit 28 ch, 10-bit 36 ch, 10-bit 36 ch, 10-bit 28 ch, 10-bit ctu yes total timer i/o 3 emios 3 refer to emios section of device reference manual for information on the channel configuration and functions 28 ch, 16-bit 56 ch, 16-bit 28 ch, 16-bit 28 ch, 16-bit 56ch, 16-bit 28 ch, 16-bit 28 ch, 16-bit 56 ch, 16-bit 56 ch, 16-bit 28 ch, 16-bit ? pwm + mc + ic/oc 4 4 ic - input capture; oc - output compare; pwm - pulse width modulation; mc - modulus counter 5ch 10ch 5ch 5ch 10ch 5ch 5ch 10ch 10ch 5ch ? pwm + ic/oc 4 20 ch 40 ch 20 ch 20 ch 40 ch 20 ch 20 ch 40 ch 40 ch 20 ch ? ic/oc 4 3ch 6ch 3ch 3ch 6ch 3ch 3ch 6ch 6ch 3ch sci (linflex)3444 4 4 spi (dspi) 3 can (flexcan) 26363366 i 2 c1 32 khz oscillator ye s gpio 5 5 i/o count based on multiplexing with peripherals 79 123 79 79 123 79 79 123 123 79 debug jtag nexus2+ jtag package 100 lqfp 144 lqfp 100 lqfp 100 lqfp 144 lqfp 100 lqfp 100 lqfp 144 lqfp 208 map bga 6 6 208 mapbga available only as development package for nexus2+ 100 lqfp MPC5604B/c microcontrolle r data sheet, rev. 2 preliminary?subject to change without notice freescale semiconductor 5 2 device blocks 2.1 block diagram figure 1 shows a top-level block diagram of the MPC5604B/c device series. figure 1. MPC5604B/c series block diagram 3 x dspi fmpll tcu nexus 2+ nexus ram siu reset control 48 kb external imux gpio & jtag pad control jtag port nexus port e200z0h interrupt blocks 64-bit 2 x 3 crossbar switch 6 x flexcan peripheral bridges peripheral requests from interrupt request interrupt request i/o clocks instructions data voltage regulator nmi swt pit stm nmi siu . . . . . . . . . . . . intc i 2 c . . . 4 x linflex 2 x emios 36 ch. adc mpu cmu sram flash code flash 512 kb dataflash 64 kb pcu mem cgm rgm bam ctu rtc sscm (master) (master) (slave) (slave) (slave) controller controller legend: adc analog-to-digital converter bam boot assist module can controller area network (flexcan) cgm clock generation module cmu clock monitor unit ctu cross triggering unit dspi deserial serial peripheral interface emios enhanced modular input output system fmpll frequency-modulated phase-locked loop i2c inter-integrated circuit bus imux internal multiplexer intc interrupt controller jtag jtag controller linflex serial communication interface (lin support) mem mode entry module mpu memory protection unit nexus nexus development interface (ndi) level nmi non-maskable interrupt pcu power control unit pit periodic interrupt timer rgm reset generation module rtc real-time clock siu system integration unit sram static random-access memory sscm system status configuration module stm system timer module swt software watchdog timer tcu test control unit MPC5604B/c microcontrolle r data sheet, rev. 2 preliminary?subject to change without notice freescale semiconductor 6 2.2 device block summary table 2 summarizes the functions of all blocks present in the mp c5604b/c series of microcontrollers. please note that the presence and number of blocks varies by device and package. table 2. MPC5604B/c series block summary block function crossbar (xbar) switch supports simultaneous connections between two master ports and three slave ports. the crossbar supports a 32-bit address bus width and a 64-bit data bus width analog-to-digital converter (adc) multi-channel, 10-bit analog-to digital-converter boot assist module (bam) a block of read-only memory containing vle code which is executed according to the boot mode of the device clock generation module (cgm) provides logic and control required for the gen eration of system and peripheral clocks clock monitor unit (cmu) monitors clock source (internal and external) integrity cross triggering unit (ctu) enables synchronization of adc conversions with a timer event from the emios or from the pit deserial serial peripheral interface (dspi) provides a synchronous serial interface for communication with external devices enhanced modular input output system (emios) provides the functionality to generate or measure events flash memory provides non-volatile storage for program code, constants and variables flexcan (controller area network) supports the standard can communications protocol fmpll (frequency-modulated phase-locked loop) generates high-speed system clocks and supports programmable frequency modulation internal multiplexer (imux) siu subblock allows flexible mapping of peripheral interface on the different pins of the device inter-integrated circuit (i 2 c?) bus a two wire bidirectional serial bus that provides a simple and efficient method of data exchange between devices interrupt controller (intc) provides priority-based preemptive scheduling of interrupt requests jtag controller provides the means to test chip functionality and connectivity while remaining transparent to syst em logic when not in test mode linflex controller manages a high number of lin (local interconnect network protocol) messages efficiently with a minimum of cpu load memory protection unit (mpu) provides hardware access control for all memory references generated in a device mode entry module (mem) provides a mechanism for c ontrolling the device operational mode and mode transition sequences in all functional st ates; also manages the power control unit, reset generation module and clock generation module, and holds the configuration, control and status registers accessible for applications non-maskable interrupt (nmi) handles external events t hat must produce an immediate response, such as power down detection nexus development interface (ndi) level provides real-time development support capabilities in compliance with the ieee-isto 5001-2003 standard MPC5604B/c microcontrolle r data sheet, rev. 2 preliminary?subject to change without notice freescale semiconductor 7 periodic interrupt timer (pit) produces periodic interrupts and triggers power control unit (pcu) reduces the overall power consumption by disconnecting parts of the device from the power supply via a power switching device; device components are grouped into sections called ?power domains? which are controlled by the pcu real-time counter (rtc) a free running counter used for time keeping applications, the rtc can be configured to generate an interrupt at a predefined interval independent of the mode of operation (run mode or low-power mode) reset generation module (rgm) centralizes reset sources and manages the device reset sequence of the device static random-access memory (sram) provides storage for program code, constants, and variables system integration unit (siu) provides control over all the electrical pad controls and up 32 ports with 16 bits of bidirectional, general-purpose input and output signals and supports up to 32 external interrupts with trigger event configuration system status configuration module (sscm) provides system configurati on and status data (such as memory size and status, device mode and security status, dma st atus), device identification data, debug status port enable and selection, and bus and peripheral abort enable/disable system timer module (stm) provides a set of output compare events to support autosar and operating system tasks system watchdog timer (swt) provides protection from runaway code test control unit (tcu) an extension of the jtag cont roller module, the tcu provides the means to test chip functionality and connectivity while remaining transparent to system logic when not in test mode. table 2. MPC5604B/c series block summary (continued) block function MPC5604B/c microcontrolle r data sheet, rev. 2 preliminary?subject to change without notice freescale semiconductor 8 3 package pinouts the available lqfp pinouts and the 208 mapbga ballmap are provided in the following figures. for pin signal descriptions, please refer to the device reference manual. figure 2. lqfp 144-pin configuration (top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 wkup[11] / scl / lin0rx / gpio[19] / pb[3] wkup[13] / lin2rx / gpio[41] / pc[9] eirq[8] / sck2 / e0uc[14] / gpio[46] / pc[14] cs0_2 / e0uc[15] / gpio[47] / pc[15] wkup[18] / e1uc[14] / gpio[101] / pg[5] e1uc[13] / gpio[100] / pg[4] wkup[17] / e1uc[12] / gpio[99] / pg[3] e1uc[11] / gpio[98] / pg[2] wkup[3] / e0uc[2] / gpio[2] / pa[2] wkup[6] / can5rx / e0uc[16] / gpio[64] / pe[0] wkup[2] / nmi / e0uc[1] / gpio[1] / pa[1] can5tx / e0uc[17] / gpio[65] / pe[1] can3tx / e0uc[22] / can2tx / gpio[72] / pe[8] wkup[7] / e0uc[23] / can3rx / can2rx / gpio[73] / pe[9] eirq[10] / cs3_1 / lin3tx / gpio[74] / pe[10] wkup[19] / clkout / e0uc[0] / gpio[0] / pa[0] wkup[14] / cs4_1 / lin3rx / gpio[75] / pe[11] vss_hv vdd_hv vss_hv reset vss_lv vdd_lv vdd_bv sck_2 / e1uc[18] / gpio[105] / pg[9] eirq[15] / cs0_2 / e1uc[17] / gpio[104] / pg[8] wkup[5] / can4rx / can1rx / gpio[43] / pc[11] ma[1] / can4tx / can1tx / gpio[42] / pc[10] e1uc[16] / gpio[103] / pg[7] e1uc[15] / gpio[102] / pg[6] can0tx / gpio[16] / pb[0] wkup[4] / can0rx / gpio[17] / pb[1] cs5_0 / can3rx / can2rx / gpio[89] / pf[9] cs4_0 / can3tx / can2tx / gpio[88] / pf[8] e1uc[25] / gpio[92] / pf[12] lin1tx / gpio[38] / pc[6] pa[11] / gpio[11] / e0uc[11] / scl pa[10] / gpio[10] / e0uc[10] / sda pa[9] / gpio[9] / e0uc[9] / fab pa[8] / gpio[8] / e0uc[8] / lin3rx / eirq[3] / abs[0] pa[7] / gpio[7] / e0uc[7] / lin3tx / eirq[2] pe[13] / gpio[77] / sout2 / e1uc[20] pf[14] / gpio[94] / can1tx / can4tx / e1uc[27] pf[15] / gpio[95] / can1rx / can4rx / eirq[13] vdd_hv vss_hv pg[0] / gpio[96] / can5tx / e1uc[23] pg[1] / gpio[97] / can5rx / e1uc[24] / eirq[14] ph[3] / gpio[115] / e1uc[5] / cs0_1 ph[2] / gpio[114] / e1uc[4] / sck1 ph[1] / gpio[113] / e1uc[3] / sout1 ph[0] / gpio[112] / e1uc[2] / sin1 pg[12] / gpio[108] / e0uc[26] pg[13] / gpio[109] / e0uc[27] pa[3] / gpio[3] / e0uc[3] / eirq[0] pb[15] / gpio[31] / cs4_0 / e0uc[7] / anx[3] pd[15] / gpio[63] / cs2_1 / ans[7] / e0uc[27] pb[14] / gpio[30] / cs3_0 / e0uc[6] / anx[2] pd[14] / gpio[62] / cs1_1 / ans[6] / e0uc[26] pb[13] / gpio[29] / cs2_0 / e0uc[5] / anx[1] pd[13] / gpio[61] / cs0_1 / ans[5] / e0uc[25] pb[12] / gpio[28] / cs1_0 / e0uc[4] / anx[0] pd[12] / gpio[60] / cs5_0 / ans[4] / e0uc[24] pb[11] / gpio[27] / e0uc[3] / ans[3] / cs0_0 pd[11] / gpio[59] / anp[15] pd[10] / gpio[58] / anp[14] pd[9] / gpio[57] / anp[13] pb[7] / gpio[23] / anp[3] pb[6] / gpio[22] / anp[2] pb[5] / gpio[21] / anp[1] vdd_hv_adc vss_hv_adc wkup[12] / lin1rx / gpio[39] / pc[7] gpio[90] / pf[10] wkup[15] / gpio[91] / pf[11] wkup[10] / sck_0 / cs0_0 / gpio[15] / pa[15] wkup[16] / e1uc[26] / gpio[93] / pf[13] eirq[4] / cs0_0 / sck_0 / gpio[14] / pa[14] wkup[9] / e0uc[4] / gpio[4] / pa[4] sout_0 / gpio[13] / pa[13] sin_0 / gpio[12] / pa[12] vdd_lv vss_lv xtal vss_hv extal vdd_hv osc32k_extal / ans[1] / gpio[25] / pb[9] osc32k_xtal / ans[0] / gpio[24] / pb[8] wkup[8] / ans[2] / gpio[26] / pb[10] cs3_1 / ans[8] / e0uc[10] / gpio[80] / pf[0] cs4_1 / ans[9] / e0uc[11] / gpio[81] / pf[1] cs0_2 / ans[10] / e0uc[12] / gpio[82] / pf[2] cs1_2 / an1[11] / e0uc[13] / gpio[83] / pf[3] cs2_2 / ans[12] / e0uc[14] / gpio[84] / pf[4] cs3_2 / ans[13] / e0uc[22] / gpio[85] / pf[5] ans[14] / e0uc[23] / gpio[86] / pf[6] ans[15] / gpio[87] / pf[7] anp[4] / gpio[48] / pd[0] anp[5] / gpio[49] / pd[1] anp[6] / gpio[50] / pd[2] anp[7] / gpio[51] / pd[3] anp[8] / gpio[52] / pd[4] anp[9] / gpio[53] / pd[5] anp[10] / gpio[54] / pd[6] anp[11] / gpio[55] / pd[7] anp[12] / gpio[56] / pd[8] anp[0] / gpio[20] / pb[4] pb[2] / gpio[18] / lin0tx / sda pc[8] / gpio[40] / lin2tx pc[13] / gpio[45] / e0uc[13] / sout_2 pc[12] / gpio[44] / e0uc[12] / sin_2 pe[7] / gpio[71] / e0uc[23] / cs2_0 / ma[0] pe[6] / gpio[70] / e0uc[22] / cs3_0 / ma[1] ph[8] / gpio[120] / e1uc[10] / cs2_2 / ma[0] ph[7] / gpio[119] / e1uc[9] / cs3_2 / ma[1] ph[6] / gpio[118] / e1uc[8] ma[2] ph[5] / gpio[117] / e1uc[7] ph[4] / gpio[116] / e1uc[6] pe[5] / gpio[69] / e0uc[21] / cs0_1 / ma[2] pe[4] / gpio[68] / e0uc[20] / sck_1 / eirq[9] pc[4] / gpio[36] / sin_1 / can3rx pc[5] / gpio[37] / sout_1 / can3tx / eirq[7] pe[3] / gpio[67] / e0uc[19] / sout_1 pe[2] / gpio[66] / e0uc[18] / sin_1 ph[9] / gpio[121] / tck pc[0] / gpio[32] / tdi vss_lv vdd_lv vdd_hv vss_hv pc[1] / gpio[33] / tdo ph[10] / gpio[122] / tms pa[6] / gpio[6] / e0uc[6] / eirq[1] pa[5] / gpio[5] / e0uc[5] pc[2] / gpio[34] / sck_1 / can4tx / eirq[5] pc[3] / gpio[35] / cs0_1 / ma[0] / can1rx / can4rx / eirq[6] pg[11] / gpio[107] / e0uc[25] pg[10] / gpio[106] / e0uc[24] pe[15] / gpio[79] / cs0_2 / e1uc[22] pe[14] / gpio[78] / sck_2 / e1uc[21] / eirq[12] pg[15] / gpio[111] / e1uc[1] pg[14] / gpio[110] / e1uc[0] pe[12] / gpio[76] / sin_2 / e1uc[19] / eirq[11] 144 lqfp note: availability of port pin alternate functions depends on product selection. MPC5604B/c microcontrolle r data sheet, rev. 2 preliminary?subject to change without notice freescale semiconductor 9 figure 3. lqfp 100-pin configuration (top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 wkup[11] / scl / lin0rx / gpio[19] / pb[3] wkup[13] / lin2rx / gpio[41] / pc[9] eirq[8] / sck2 / e0uc[14] / gpio[46] / pc[14] cs0_2 / e0uc[15] / gpio[47] / pc[15] wkup[3] / e0uc[2] / gpio[2] / pa[2] wkup[6] / can5rx / e0uc[16] / gpio[64] / pe[0] wkup[2] / nmi / e0uc[1] / gpio[1] / pa[1] can5tx / e0uc[17] / gpio[65] / pe[1] can3tx / e0uc[22] /can2tx / gpio[72] / pe[8] wkup[7] / can3rx / e0uc[23] /can2rx / gpio[73] / pe[9] eirq[10] / cs3_1 / lin3tx / gpio[74] / pe[10] wkup[19] / clkout / e0uc[0] / gpio[0] / pa[0] wkup[14] / cs4_1 / lin3rx / gpio[75] / pe[11] vss_hv vdd_hv vss_hv reset vss_lv vdd_lv vdd_bv wkup[5] / can4rx / can1rx / gpio[43] / pc[11] ma[1] / can4tx / can1tx / gpio[42] / pc[10] can0tx / gpio[16] / pb[0] wkup[4] / can0rx / gpio[17] / pb[1] lin1tx / gpio[38] / pc[6] pa[11] / gpio[11] / e0uc[11] / scl pa[10] / gpio[10] / e0uc[10] / sda pa[9] / gpio[9] / e0uc[9] / fab pa[8] / gpio[8] / e0uc[8] / lin3rx / eirq[3] / abs[0] pa[7] / gpio[7] / e0uc[7] / lin3tx / eirq [2] vdd_hv vss_hv pa[3] / gpio[3] / e0uc[3] / eirq[0] pb[15] / gpio[31] / cs4_0 / e0uc[7] / anx[3] pd[15] / gpio[63] / cs2_1 / ans[7] / e0uc[27] pb[14] / gpio[30] / cs3_ 0 / e0uc[6] / anx[2] pd[14] / gpio[62] / cs1_1 / ans[6] / e0uc[26] pb[13] / gpio[29] / cs2_0 / e0uc[5] / anx[1] pd[13] / gpio[61] / cs0_1 / ans[5] / e0uc[25] pb[12] / gpio[28] / cs1_0 / e0uc[4] / anx[0] pd[12] / gpio[60] / cs5_0 / ans[4] / e0uc[24] pb[11] / gpio[27] / e0uc[3] / ans[3] / cs0_0 pd[11] / gpio[59] / anp[15] pd[10] / gpio[58] / anp[14] pd[9] / gpio[57] / anp[13] pb[7] / gpio[23] / anp[3] pb[6] / gpio[22] / anp[2] pb[5] / gpio[21] / anp[1] vdd_hv_adc vss_hv_adc wkup[12] / lin1rx / gpio[39] / pc[7] wkup[10] / sck0 / cs0_0 / gpio[15] / pa[15] eirq[4] / cs0_0 / sck0 / gpio[14] / pa[14] wkup[9] / e0uc[4] / gpio[4] / pa[4] sout_0 / gpio[13] / pa[13] sin_0 / gpio[12] / pa[12] vdd_lv vss_lv xtal vss_hv extal vdd_hv osc32k_extal / ans[1] / gpio[25] / pb[9] osc32k_xtal / ans[0] / gpio[24] / pb[8] wkup[8] / ans[2] / gpio[26] / pb[10] anp[4] / gpio[48] / pd[0] anp[5] / gpio[49] / pd[1] anp[6] / gpio[50] / pd[2] anp[7] / gpio[51] / pd[3] anp[8] / gpio[52] / pd[4] anp[9] / gpio[53] / pd[5] anp[10] / gpio[54] / pd[6] anp[11] / gpio[55] / pd[7] anp[12] / gpio[56] / pd[8] anp[0] / gpio[20] / pb[4] pb[2] / gpio[18] / lin0tx / sda pc[8] / gpio[40] / lin2tx pc[13] / gpio[45] / e0uc[13] / sout_2 pc[12] / gpio[44] / e0uc[12] / sin_2 pe[7] / gpio[71] / e0uc[23] / cs2_0 / ma[0] pe[6] / gpio[70] / e0uc[22] / cs3_0 / ma[1] pe[5] / gpio[69] / e0uc[21] / cs0_1 / ma[2] pe[4] / gpio[68] / e0uc[20] / sck_1 / eirq[9] pc[4] / gpio[36] / sin1 / can3rx pc[5] / gpio[37] / sout_1 / can3tx / eirq[7] pe[3] / gpio[67] / e0uc[19] / sout_1 pe[2] / gpio[66] / e0uc[18] / sin_1 ph[9] / gpio[121] / tck pc[0] / gpio[32] / tdi vss_lv vdd_lv vdd_hv vss_hv pc[1] / gpio[33] / tdo ph[10] / gpio[122] / tms pa[6] / gpio[6] / e0uc[6] / eirq[1] pa[5] / gpio[5] / e0uc[5] pc[2] / gpio[34] / sck1 / can4tx / eirq[5] pc[3] / gpio[35] / cs0_1 / ma[0] / can1rx / can4rx / eirq[6] pe[12] / gpio[76] / sin_2 / eirq[11] 100 lqfp note: availability of port pin alternate functions depends on product selection. MPC5604B/c microcontrolle r data sheet, rev. 2 preliminary?subject to change without notice freescale semiconductor 10 figure 4. 208 mapbga configuration 1,2 1. nc = not connected 2. 208 mapbga available only as de velopment package for nexus2+ MPC5604B/c microcontrolle r data sheet, rev. 2 preliminary?subject to change without notice freescale semiconductor 11 4 electrical characteristics 4.1 introduction this section contains electrical char acteristics of the device as well as temperature and power considerations. this product contains devices to protect the inputs against damage due to high static voltages. however, it is advisable to tak e precautions to avoid application of any voltage higher than the specified maximum rated voltages. to enhance reliability, unused inputs can be driven to an appropriate logic voltage level (v dd or v ss ). this could be done by the internal pull-up and pull-down, which is provided by the product for most general purpose pins. the parameters listed in the following tables represent th e characteristics of the device and its demands on the system. in the tables where the device lo gic provides signals with their respective timing characteristics, the symbol ?cc? for control ler characteristics is included in the symbol column. in the tables where the external system mu st provide signals with their respective timing characteristics to the device, the sy mbol ?sr? for system requirement is included in the symbol column. caution all of the following figures are indicative and must be confirmed during either sili con validation, silicon characterization or silicon reliability trial. 4.2 parameter classification the electrical parameters shown in this supplement are guaranteed by various methods. to give the customer a better understanding, the classifications listed in table 3 are used and the parameters are ta gged accordingly in the tables where appropriate. note the classification is shown in the column labeled ?c? in the parameter tables where appropriate. 4.3 nvusro register portions of the device configuration, such as high voltage supp ly, oscillator margin, and watch dog enable/disable after reset a re controlled via bit values in the non-volatile user options register (nvusro) register. 4.3.1 nvusro[pad3v5v] field description table 4 shows how nvusro[pad3v5v] controls the device configuration. table 3. parameter classifications classification ta g tag description p those parameters are guaranteed during production testing on each individual device. c those parameters are achieved by the design characterization by measuring a statistically relevant sample size across process variations. t those parameters are achieved by design characterization on a small sample size from typical devices under typical conditions unless otherwise noted. all values shown in the typical column are within this category. d those parameters are derived mainly from simulations. MPC5604B/c microcontrolle r data sheet, rev. 2 preliminary?subject to change without notice freescale semiconductor 12 the dc electrical characteristics are dependent on the pad3v5v bit value. 4.3.2 nvusro[oscillator_margin] field description table 5 shows how nvusro[oscillator_margin] controls the device configuration. the fast external crystal oscillator consumptio n is dependent on the osci llator_margin bit value. 4.4 absolute maximum ratings table 4. pad3v5v field description 1 1 see the device reference manual for more information on the nvusro register. value 2 2 default manufacturing value before flash initialization is ?1? (3.3 v) description 0 high voltage supply is 5.0 v 1 high voltage supply is 3.3 v table 5. oscillator_margin field description 1 1 see the device reference manual for more information on the nvusro register. value 2 2 default manufacturing value before flash initialization is ?1? description 0 low consumption configuration (4 mhz/8 mhz) 1 high margin configuration (4 mhz/16 mhz) table 6. absolute maximum ratings symbol parameter conditions value unit min max v ss sr digital ground on vss_hv pins 0 0 v v dd sr voltage on vdd_hv pins with respect to ground (v ss ) ? 0.3 6.0 v v ss_lv sr voltage on vss_lv (l ow voltage digital supply) pins with respect to ground (v ss ) v ss ? 0.1 v ss +0.1 v v dd_bv sr voltage on vdd_bv pin (regulator supply) with respect to ground (v ss ) ? 0.3 5.5 v relative to v dd ? 0.3 v dd +0.3 v ss_adc sr voltage on vss_hv_adc (adc reference) pin with respect to ground (v ss ) v ss ? 0.1 v ss +0.1 v v dd_adc sr voltage on vdd_hv_adc pin (adc reference) with respect to ground (v ss ) ? 0.3 5.5 v relative to v dd ? 0.3 v dd +0.3 v in sr voltage on any gpio pin with respect to ground (v ss ) ? 0.3 5.5 v relative to v dd ? 0.3 v dd +0.3 MPC5604B/c microcontrolle r data sheet, rev. 2 preliminary?subject to change without notice freescale semiconductor 13 note stresses exceeding the recommended absolute maximum ratings ma y cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indi cated in the operational sections of this specification are not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. during overload conditions (v in >v dd or v in MPC5604B/c microcontrolle r data sheet, rev. 2 preliminary?subject to change without notice freescale semiconductor 15 note ram data retention is guaranteed with v dd_lv not below 1.08 v. 4.6 thermal characteristics 4.6.1 package thermal characteristics i injpad sr injected input current on any pin during overload condition ? 55ma i injsum sr absolute sum of all injected input currents during overload condition ? 50 50 tv dd sr v dd slope to ensure correct power up 6 ?0.25v/s 3?v/s t a sr ambient temperature under bias f cpu < 60 mhz ? 40 125 c f cpu < 64 mhz ? 40 105 t j sr junction temperature under bias ? 40 150 1 100 nf capacitance needs to be provided between each v dd /v ss pair. 2 full device operation is guaranteed by design when the voltage drops below 4.5v down to 3.6v. however, certain analog electrical characteristics will not be guaranteed to stay wit hin the stated limits. 3 330 nf capacitance needs to be provided between each v dd_lv /v ss_lv supply pair. 4 100 nf capacitance needs to be provided between v dd_bv and the nearest v ss_lv (higher value may be needed depending on external regulator characteristics). 5 100 nf capacitance needs to be provided between v dd_adc /v ss_adc pair. 6 guaranteed by device validation table 9. lqfp thermal characteristics 1 1 thermal characteristics are targets based on simulation that are subject to change per device characterization. symbol c parameter conditions 2 2 v dd = 3.3 v 10% / 5.0 v 10%, t a = ? 40 to 125 c. pin count value 3 3 all values need to be confirmed during device validation. unit min typ max r ja cc d thermal resistance, junction-to-ambient natural convection 4 4 junction-to-ambient thermal resistance determined per je dec jesd51-3 and jesd51-6. thermal test board meets jedec specification for this package. when greek lett ers are not available, the symbols are typed as r thja and r thjma . single-layer board?1s 100 64 c/w 144 64 four-layer board?2s2p 100 50.8 144 49.4 table 8. recommended operating conditions (5.0 v) (continued) symbol parameter conditions value unit min max MPC5604B/c microcontrolle r data sheet, rev. 2 preliminary?subject to change without notice freescale semiconductor 16 4.6.2 power considerations the average chip-junction temperature, t j , in degrees celsius, may be calculated using equation 1 : t j = t a + (p d x r ja ) eqn. 1 where: t a is the ambient temperature in c. r ja is the package junction-to-ambie nt thermal resistance, in c/w. p d is the sum of p int and p i/o (p d = p int + p i/o ). p int is the product of i dd and v dd , expressed in watts. this is the chip internal power. p i/o represents the power dissipation on input and output pins; user determined. most of the time for the applications, p i/o < p int and may be neglected. on the other hand, p i/o may be significant, if the device is configured to continuously drive external modules and/or memories. an approximate relationship between p d and t j (if p i/o is neglected) is given by: p d = k / (t j + 273 c) eqn. 2 therefore, solving equations 1 and 2 : k = p d x (t a + 273 c) + r ja x p d 2 eqn. 3 where: k is a constant for the particular part, which may be determined from equation 3 by measuring p d (at equilibrium) for a known t a. using this value of k, the values of p d and t j may be obtained by solving equations 1 and 2 iteratively for any value of t a . 4.7 i/o pad electrical characteristics 4.7.1 i/o pad types the device provides four main i/o pad types depe nding on the associated alternate functions: ? slow pads?these pads are the most common pads, providing a good compromise between transition time and low electromagnetic emission. ? medium pads?these pads provide transition fast enough for the serial communicati on channels with controlled current to reduce elect romagnetic emission. ? fast pads?these pads provide maximum speed. there are used for improved nexus debugging capability. table 10. 208 mapbga thermal characteristics 1 1 thermal characteristics are targets based on simulation that are subject to change per device characterization. symbol c parameter conditions value unit r ja cc ? thermal resistance, junction-to-ambient natural convection 2 2 junction-to-ambient thermal resistance determined per je dec jesd51-3 and jesd51-6. thermal test board meets jedec specification for this package. when greek le tters are not available, the symbols are typed as r thja and r thjma . single-layer board?1s tbd c/w four-layer board?2s2p MPC5604B/c microcontrolle r data sheet, rev. 2 preliminary?subject to change without notice freescale semiconductor 17 ? input only pads?these pads are associ ated to adc channels and 32 khz slow external crystal oscillator providing low input leakage. medium and fast pads can use slow configuration to reduce elect romagnetic emission, at the cost of reducing ac performance. 4.7.2 i/o input dc characteristics table 11 provides input dc electrical characteristics as described in figure 5 . figure 5. i/o input dc electrical characteristics definition table 11. i/o input dc electrical characteristics symbol c parameter conditions 1 1 v dd = 3.3 v 10% / 5.0 v 10%, t a = ? 40 to 125 c, unless otherwise specified value 2 2 all values need to be confirmed during device validation. unit min typ max v ih sr p input high level cmos (schmitt trigger) 0.65v dd v dd +0.4 v v il sr p input low level cmos (schmitt trigger) ? 0.4 0.35v dd v hys cc c input hysteresis cmos (schmitt trigger) 0.1v dd i lkg cc p digital input leakage no injection on adjacent pin t a = ? 40 c 2 ? na pt a =25 c 2 ? dt a = 105 c 12 500 pt a = 125 c 70 1000 w fi sr p digital input filtered pulse 40 ns w nfi sr p digital input not filtered pulse 1000 ns v il v in v ih pdix = ?1? v dd v hys (gpdi register of siul) pdix = ?0? MPC5604B/c microcontrolle r data sheet, rev. 2 preliminary?subject to change without notice freescale semiconductor 18 4.7.3 i/o output dc characteristics the following tables provide dc char acteristics for bidirectional pads: ? table 12 provides weak pull figures. both pull- up and pull-down resistances are supported. ? table 13 provides output driver char acteristics for i/o pads wh en in slow configuration. ? table 14 provides output driver char acteristics for i/o pads when in medium configuration. ? table 15 provides output driver char acteristics for i/o pads wh en in fast configuration. table 12. i/o pull-up/pull-down dc electrical characteristics symbol c parameter conditions 1 1 v dd = 3.3 v 10% / 5.0 v 10%, t a = ? 40 to 125 c, unless otherwise specified. value unit min typ max |i wpu | cc p weak pull-up current absolute value v in = v il , v dd = 5.0 v 10% pad3v5v = 0 10 150 a cpad3v5v = 1 2 2 the configuration pad3v5 = 1 when v dd = 5 v is only a transient co nfiguration during power- up. all pads but reset and nexus output (mdox, evto, mcko) are config ured in input or in high impedance state. 10 250 pv in = v il , v dd = 3.3 v 10% pad3v5v = 1 10 150 |i wpd | cc p weak pull-down current absolute value v in = v ih , v dd = 5.0 v 10% pad3v5v = 0 10 150 a c pad3v5v = 1 10 250 pv in = v ih , v dd = 3.3 v 10% pad3v5v = 1 10 150 table 13. slow configuration output buffer electrical characteristics symbol c parameter conditions 1 1 v dd = 3.3 v 10% / 5.0 v 10%, t a = ? 40 to 125 c, unless otherwise specified value unit min typ max v oh cc p output high level slow configuration push pull i oh = ? 2ma, v dd = 5.0 v 10%, pad3v5v = 0 (recommended) 0.8v dd v ci oh = ? 2ma, v dd = 5.0 v 10%, pad3v5v = 1 2 2 the configuration pad3v5 = 1 when v dd = 5 v is only a transient c onfiguration during power-up. all pads but reset and nexus output (mdox, evto, mcko) are configured in input or in high impedance state. 0.8v dd ci oh = ? 1ma, v dd = 3.3 v 10%, pad3v5v = 1 (recommended) v dd ? 0.8 v ol cc p output low level slow configuration push pull i ol = 2 ma, v dd = 5.0 v 10%, pad3v5v = 0 (recommended) 0.1v dd v ci ol = 2 ma, v dd = 5.0 v 10%, pad3v5v = 1 (2) 0.1v dd ci ol = 1 ma, v dd = 3.3 v 10%, pad3v5v = 1 (recommended) 0.5 MPC5604B/c microcontrolle r data sheet, rev. 2 preliminary?subject to change without notice freescale semiconductor 19 table 14. medium configuration output buffer electrical characteristics symbol c parameter conditions 1 1 v dd = 3.3 v 10% / 5.0 v 10%, t a = ? 40 to 125 c, unless otherwise specified value unit min typ max v oh cc c output high level medium configuration push pull i oh = ? 3.8 ma, v dd = 5.0 v 10%, pad3v5v = 0 0.8v dd v pi oh = ? 2ma, v dd = 5.0 v 10%, pad3v5v = 0 (recommended) 0.8v dd ci oh = ? 1ma, v dd = 5.0 v 10%, pad3v5v = 1 2 2 the configuration pad3v5 = 1 when v dd = 5 v is only a transient configuration during power-up. all pads but reset and nexus output (mdox, evto, mcko) are configured in input or in high impedance state. 0.8v dd ci oh = ? 1ma, v dd = 3.3 v 10%, pad3v5v = 1 (recommended) v dd ? 0.8 ci oh = ? 100 a, v dd = 5.0 v 10%, pad3v5v = 0 0.8v dd v ol cc c output low level medium configuration push pull i ol = 3.8 ma, v dd = 5.0 v 10%, pad3v5v = 0 0.2v dd v pi ol = 2 ma, v dd = 5.0 v 10%, pad3v5v = 0 (recommended) 0.1v dd ci ol = 1 ma, v dd = 5.0 v 10%, pad3v5v = 1 (2) 0.1v dd ci ol = 1 ma, v dd = 3.3 v 10%, pad3v5v = 1 (recommended) 0.5 ci oh = 100 a, v dd = 5.0 v 10%, pad3v5v = 0 0.1v dd table 15. fast configuration output buffer electrical characteristics symbol c parameter conditions 1 value unit min typ max v oh cc p output high level fast configuration push pull i oh = ? 14ma, v dd = 5.0 v 10%, pad3v5v = 0 (recommended) 0.8v dd v ci oh = ? 7ma, v dd = 5.0 v 10%, pad3v5v = 1 2 0.8v dd ci oh = ? 11ma, v dd = 3.3 v 10%, pad3v5v = 1 (recommended) v dd ? 0.8 MPC5604B/c microcontrolle r data sheet, rev. 2 preliminary?subject to change without notice freescale semiconductor 20 4.7.4 output pin transition times v ol cc p output low level fast configuration push pull i ol = 14ma, v dd = 5.0 v 10%, pad3v5v = 0 (recommended) 0.1v dd v ci ol = 7ma, v dd = 5.0 v 10%, pad3v5v = 1 (2) 0.1v dd ci ol = 11ma, v dd = 3.3 v 10%, pad3v5v = 1 (recommended) 0.5 1 v dd = 3.3 v 10% / 5.0 v 10%, t a = ? 40 to 125 c, unless otherwise specified 2 the configuration pad3v5 = 1 when v dd = 5 v is only a transient configuration during power-up. all pads but reset and nexus output (mdox, evto, mcko) are c onfigured in input or in high impedance state. table 16. output pin transition times symbol c parameter conditions 1 1 v dd = 3.3 v 10% / 5.0 v 10%, t a = ? 40 to 125 c, unless otherwise specified value 2 unit min typ max t tr cc d output transition time output pin 3 slow configuration c l = 25 pf v dd = 5.0 v 10%, pad3v5v = 0 50 ns tc l = 50 pf 100 dc l = 100 pf 125 dc l = 25 pf v dd = 3.3 v 10%, pad3v5v = 1 50 tc l = 50 pf 100 dc l = 100 pf 125 t tr cc d output transition time output pin (3) medium configuration c l = 25 pf v dd = 5.0 v 10%, pad3v5v = 0 10 ns tc l = 50 pf 20 dc l = 100 pf 40 dc l = 25 pf v dd = 3.3 v 10%, pad3v5v = 1 12 tc l = 50 pf 25 dc l = 100 pf 40 t tr cc d output transition time output pin (3) fast configuration c l = 25 pf v dd = 5.0 v 10%, pad3v5v = 0 4ns c l = 50 pf 6 c l = 100 pf 12 c l = 25 pf v dd = 3.3 v 10%, pad3v5v = 1 4 c l = 50 pf 7 c l = 100 pf 12 table 15. fast configuration output buffer electrical characteristics (continued) symbol c parameter conditions 1 value unit min typ max MPC5604B/c microcontrolle r data sheet, rev. 2 preliminary?subject to change without notice freescale semiconductor 21 4.7.5 i/o pad current specification the i/o pads are distributed across the i/o supply segm ent. each i/o supply segm ent is associated to a v dd /v ss supply pair as described in table 17 . table 18 provides i/o consumption figures. in order to ensure device reliability, the average current of the i/o on a si ngle segment should remain below the i av g s e g maximum value. in order to ensure device functionality, the sum of the dynamic and static current of the i/o on a single segment should remain below the i dynseg maximum value. 2 all values need to be confirmed during device validation. 3 c l includes device and package capacitances (c pkg < 5 pf). table 17. i/o supply segment package supply segment 123456 208 mapbga 1 1 208 mapbga available only as de velopment package for nexus2+ equivalent to 144 lqfp segment pad distribution mcko mdon/mseo 144 lqfp pin20?pin49 pin51?pin99 pin100?pin122 pin 123?pin19 100 lqfp pin16?pin35 pin37?pin69 pin70?pin83 pin 84?pin15 table 18. i/o consumption symbol c parameter conditions 1 value 2 unit min typ max i dynseg sr d sum of all the dynamic and static i/o current within a supply segment v dd = 5.0 v 10%, pad3v5v = 0 110 ma v dd = 3.3 v 10%, pad3v5v = 1 65 i swtslw ,3 cc d dynamic i/o current for slow configuration c l = 25 pf v dd = 5.0 v 10%, pad3v5v = 0 20 ma v dd = 3.3 v 10%, pad3v5v = 1 16 i swtmed (3) cc d dynamic i/o current for medium configuration c l = 25 pf v dd = 5.0 v 10%, pad3v5v = 0 29 ma v dd = 3.3 v 10%, pad3v5v = 1 17 i swtfst (3) cc d dynamic i/o current for fast configuration c l = 25 pf v dd = 5.0 v 10%, pad3v5v = 0 110 ma v dd = 3.3 v 10%, pad3v5v = 1 50 MPC5604B/c microcontrolle r data sheet, rev. 2 preliminary?subject to change without notice freescale semiconductor 22 i rmsslw cc d root medium square i/o current for slow configuration c l = 25 pf, 2 mhz v dd = 5.0 v 10%, pad3v5v = 0 2.3 ma c l = 25 pf, 4 mhz 3.2 c l = 100 pf, 2 mhz 6.6 c l = 25 pf, 2 mhz v dd = 3.3 v 10%, pad3v5v = 1 1.6 c l = 25 pf, 4 mhz 2.3 c l = 100 pf, 2 mhz 4.7 i rmsmed cc d root medium square i/o current for medium configuration c l = 25 pf, 13 mhz v dd = 5.0 v 10%, pad3v5v = 0 6.6 ma c l = 25 pf, 40 mhz 13.4 c l = 100 pf, 13 mhz 18.3 c l = 25 pf, 13 mhz v dd = 3.3 v 10%, pad3v5v = 1 5 c l = 25 pf, 40 mhz 8.5 c l = 100 pf, 13 mhz 11 i rmsfst cc d root medium square i/o current for fast configuration c l = 25 pf, 40 mhz v dd = 5.0 v 10%, pad3v5v = 0 22 ma c l = 25 pf, 64 mhz 33 c l = 100 pf, 40 mhz 56 c l = 25 pf, 40 mhz v dd = 3.3 v 10%, pad3v5v = 1 14 c l = 25 pf, 64 mhz 20 c l = 100 pf, 40 mhz 35 i avgseg sr d sum of all the static i/o current within a supply segment v dd = 5.0 v 10%, pad3v5v = 0 70 ma v dd = 3.3 v 10%, pad3v5v = 1 65 1 v dd = 3.3 v 10% / 5.0 v 10%, t a = ? 40 to125 c, unless otherwise specified 2 all values need to be confirmed during device validation. 3 stated maximum values represent peak consumption that lasts only a few ns during i/o transition. table 18. i/o consumption (continued) symbol c parameter conditions 1 value 2 unit min typ max MPC5604B/c microcontrolle r data sheet, rev. 2 preliminary?subject to change without notice freescale semiconductor 23 4.8 nrstin electrical characteristics the device implements a dedicat ed bidirectional reset pin. figure 6. start-up reset requirements figure 7. noise filtering on reset signal v il v dd device reset forced by nrstin v ddmin nrstin v ih device start-up phase v rstin v il v ih v dd filtered by hysteresis filtered by lowpass filter w frst w nfrst hw_rst ?1? ?0? filtered by lowpass filter w frst unknown reset state device under hardware reset MPC5604B/c microcontrolle r data sheet, rev. 2 preliminary?subject to change without notice freescale semiconductor 24 table 19. reset electrical characteristics symbol c parameter conditions 1 1 v dd = 3.3 v 10% / 5.0 v 10%, t a = ? 40 to 125 c, unless otherwise specified value 2 2 all values need to be confirmed during device validation. unit min typ max v ih sr p input high level cmos (schmitt trigger) 0.65v dd v dd +0.4 v v il sr p input low level cmos (schmitt trigger) ? 0.4 0.35v dd v v hys cc c input hysteresis cmos (schmitt trigger) 0.1v dd v v ol cc p output low level push pull, i ol = 2ma, v dd = 5.0 v 10%, pad3v5v = 0 (recommended) 0.1v dd v push pull, i ol = 1ma, v dd = 5.0 v 10%, pad3v5v = 1 3 3 this is a transient configuration during power-up, up to the end of reset phase2 (refer to rgm module section of device reference manual). 0.1v dd push pull, i ol = 1ma, v dd = 3.3 v 10%, pad3v5v = 1 (recommended) 0.5 t tr cc d output transition time output pin 4 medium configuration 4 c l includes device and package capacitance (c pkg <5pf). c l = 25pf, v dd = 5.0 v 10%, pad3v5v = 0 10 ns c l = 50pf, v dd = 5.0 v 10%, pad3v5v = 0 20 c l = 100pf, v dd = 5.0 v 10%, pad3v5v = 0 40 c l = 25pf, v dd = 3.3 v 10%, pad3v5v = 1 12 c l = 50pf, v dd = 3.3 v 10%, pad3v5v = 1 25 c l = 100pf, v dd = 3.3 v 10%, pad3v5v = 1 40 w frst sr p nrstin input filtered pulse 40 ns w nfrst sr p nrstin input not filtered pulse 1000 ns |i wpu | cc p weak pull-up current absolute value v dd = 3.3 v 10%, pad3v5v = 1 10 150 a v dd = 5.0 v 10%, pad3v5v = 0 10 150 v dd = 5.0 v 10%, pad3v5v = 1 5 5 the configuration pad3v5 = 1 when v dd = 5 v is only transient configuration du ring power-up. all pads but reset and nexus output (mdox, evto, mcko) are conf igured in input or in high impedance state. 10 250 MPC5604B/c microcontrolle r data sheet, rev. 2 preliminary?subject to change without notice freescale semiconductor 25 4.9 power management electrical characteristics 4.9.1 voltage regulator electrical characteristics the device implements an internal voltage regulator to generate the low voltage core supply v dd_lv from the high voltage ballast supply v dd_bv . the regulator itself is supplied by the common i/o supply v dd . the following supplies are involved: ? hv?high voltage external power supply for voltage regulator module. this must be provided externally through v dd power pin. ? bv?high voltage external power supply for internal ballast module. this must be provided externally through v dd_bv power pin. voltage values should be aligned with v dd . ? lv?low voltage internal power supply for core, fmpll and fl ash digital logic. this is generated by the internal voltage regulator but provided outside to connect stability capacito r. it is further split into four main domains to ensure noise isolation between critical lv modules within the device: ? lv_cor?low voltage supply for the core. it is also used to provide supply for fmpll through double bonding. ? lv_cfla?low voltage supply for code flash module. it is supplied with dedicated ballast and shorted to lv_cor through double bonding. ? lv_dfla?low voltage supply for data flash module. it is supplied with dedicated ballast and shorted to lv_cor through double bonding. ? lv_pll?low voltage supply for fmpll. it is shorted to lv_cor through double bonding. figure 8. voltage regulator capacitance connection the internal voltage regulator requires external capacitance (c regn ) to be connected to the device in order to provide a stable low voltage digital supply to the device. ca pacitances should be placed on the board as near as po ssible to the associated pins . care should also be taken to limit the seri al inductance of the board to less than 5 nh. c reg1 (lv_cor/lv_dfla) device v ss_lv v dd_bv v dd_lv c dec1 (ballast decoupling) v ss_lv v dd_lv v dd v ss_lv v dd_lv c reg2 (lv_cor/lv_cfla) c reg3 (lv_cor/lv_pll) c dec2 (supply/io decoupling) device v dd_bv i v dd_lvn v ref v dd voltage regulator v ss v ss_lvn MPC5604B/c microcontrolle r data sheet, rev. 2 preliminary?subject to change without notice freescale semiconductor 26 each decoupling capacitor must be placed between each of the three v dd_lv /v ss_lv supply pairs to ensure stable voltage (see section 4.5, ?recommen ded operating conditions ). table 20. voltage regulator electrical characteristics symbol c parameter conditions 1 1 v dd = 3.3 v 10% / 5.0 v 10%, t a = ? 40 to 125 c, unless otherwise specified value 2 2 all values need to be confirmed during device validation. unit min typ max c regn sr ? internal voltage regulator external capacitance 200 330 nf r reg sr ? stability capacitor equivalent serial resistance 0.2 w c dec1 sr ? decoupling capacitance 3 ballast v dd_bv /v ss_lv pair 100 470 4 nf c dec2 sr ? decoupling capacitance regulator supply v dd /v ss pair 10 100 nf v mreg cc p main regulator output voltage before trimming 1.32 v after trimming 1.28 i mreg sr ? main regulator current provided to v dd_lv domain 200 ma i mregint cc d main regulator module current consumption i mreg = 200 ma 2 ma i mreg = 0 ma 1 v lpreg cc p low power regulator output voltage after trimming 1.23 v i lpreg sr ? low power regulator current provided to v dd_lv domain 15 ma i lpregint cc d low power regulator module current consumption i lpreg = 15 ma; t a = 55 c 600 a ? i lpreg = 0 ma; t a = 55 c 5 tbd v ulpreg cc p ultra low power regulator output voltage post trimming 1.23 v i ulpreg sr ? ultra low power regulator current provided to v dd_lv domain 5 ma i ulpregint cc d ultra low power regulator module current consumption i ulpreg = 5 ma; t a = 55 c 100 a i ulpreg = 0 ma; t a = 55 c 2 tbd i vregref cc d main lvds and reference current consumption (low power and main regulator switched off) t a = 55 c 17 a i vredlvd12 cc d main lvd current consumption (switch-off during standby) t a = 55 c 2 tbd a i dd_bv cc d in-rush current on v dd_bv during power-up 400 ma MPC5604B/c microcontrolle r data sheet, rev. 2 preliminary?subject to change without notice freescale semiconductor 27 4.9.2 voltage monitor electrical characteristics the device implements a power-on reset (por) module to ensure correct power-up initia lization, as well as four low voltage detectors (lvds) to monitor the v dd and the v dd_lv voltage while device is supplied: ? por monitors v dd during the power-up phase to ensure devi ce is maintained in a safe reset state ? lvdhv3 monitors v dd to ensure device reset below minimum functional supply ? lvdhv5 monitors v dd when application uses device in the 5.0 v 10% range ? lvdlvcor monitors power domain no. 1 ? lvdlvbkp monitors power domain no. 0 note when enabled, power domain no. 2 is monitored through lvd_digbkp. figure 9. low voltage monitor vs. reset 3 this capacitance value is driven by the constraint s of the external voltage regulator supplying the v dd_bv voltage. a typical value is in the range of 470 nf. 4 external regulator and capacitance circuitry must be capable of providing i dd_bv while maintaining supply v dd_bv in operating range. v dd v lvdhvxh reset v lvdhvxl MPC5604B/c microcontrolle r data sheet, rev. 2 preliminary?subject to change without notice freescale semiconductor 28 4.10 low voltage domain power consumption table 22 provides dc electrical characteristic s for significant application modes. th ese values are indi cative values; actual consumption depends on the application. table 21. low voltage monitor electrical characteristics symbol c parameter conditions 1 1 v dd = 3.3 v 10% / 5.0 v 10%, t a = ? 40 to 125 c, unless otherwise specified value 2 2 all values need to be confirmed during device validation. unit min typ max v porup sr p supply for functional por module t a = 25 c, after trimming 1.0 5.5 v v porh cc p power-on reset threshold 1.5 2.6 v lv d h v 3 h cc t lvdhv3 low voltage detector high threshold 2.9 v lv d h v 3 l cc p lvdhv3 low voltage detector low threshold 2.7 v lv d h v 5 h cc t lvdhv5 low voltage detector high threshold 4.4 v lv d h v 5 l cc p lvdhv5 low voltage detector low threshold 3.8 v lvd lv c o r l cc p lvdlvcor low voltage detector low threshold 1.07 1.11 v lvdlvbkpl cc p lvdlvbkp low voltage detector low threshold 1.07 1.11 table 22. low voltage power domain electrical characteristics symbol c parameter conditions 1 value unit min typ max i ddmax sr ? maximum current 150 ma i ddrun 2 cc p run mode current 80 ma i ddhalt cc p halt mode current 20 ma i ddstop cc p stop mode current slow internal rc oscillator (128 khz) running t a =25c 180 700 a dt a =55c tbd dt a =85c ct a = 105 c ct a = 125 c i ddstdby2 cc p standby2 mode current slow internal rc oscillator (128 khz) running t a =25c 30 100 a dt a =55c tbd dt a =85c ct a = 105 c ct a = 125 c MPC5604B/c microcontrolle r data sheet, rev. 2 preliminary?subject to change without notice freescale semiconductor 29 4.11 flash memory electrical characteristics 4.11.1 program/erase characteristics table 23 shows the program and erase characteristics. i ddstdby1 cc t standby1 mode current slow internal rc oscillator (128 khz) running t a =25c 20 60 a dt a =55c tbd tt a =85c dt a = 105 c dt a = 125 c 1 v dd = 3.3 v 10% / 5.0 v 10%, t a = ? 40 to 125 c, unless otherwise specified 2 running consumption is given on voltage regulator supply (v ddreg ). it does not include consumption linked to i/os toggling. this value is highly dependent on the application. the given value is thought to be a worst case value with all peripherals running, and code fetched from flash. it is to be noticed that this value can be significantly reduced by application: switch-off not used peripherals (d efault), reduce peripheral frequency through internal prescaler, fetch from ram most used functions, use low power mode when possible. table 23. program and erase specifications symbol c parameter value unit min typ 1 1 typical program and erase times assume nominal supply values and operation at 25 c. all times are subject to change pending device characterization. initial max 2 2 initial factory condition: < 100 program/erase cycles, 25 c, typical supply voltage. max 3 3 the maximum program and erase times occur after the spec ified number of program/erase cycles. these maximum values are characterized but not guaranteed. t dwprogram cc c double word (64 bits) program time 4 4 actual hardware programming times. this does not include software overhead. ?22tbd500s t 16kpperase 16 kb block pre-program and erase time ? 300 500 5000 ms t 32kpperase 32 kb block pre-program and erase time ? 400 600 5000 ms t 128kpperase 128 kb block pre-program and erase time ? 800 1300 7500 ms table 22. low voltage power domain electrical characteristics (continued) symbol c parameter conditions 1 value unit min typ max MPC5604B/c microcontrolle r data sheet, rev. 2 preliminary?subject to change without notice freescale semiconductor 30 4.11.2 flash power supply dc characteristics table 26 shows the power supply dc char acteristics on external supply. table 24. flash module life symbol c parameter conditions value unit min typ p/e cc c number of program/erase cycles per block for 16 kbyte blocks over the operating temperature range (t j ) ? 100,000 ? cycles p/e cc c number of program/erase cycles per block for 32 kbyte blocks over the operating temperature range (t j ) ? 10,000 100,000 1 1 to be confirmed cycles p/e cc c number of program/erase cycles per block for 128 kbyte blocks over the operating temperature range (t j ) ? 1,000 100,000 (1) cycles retention cc c minimum data retention at 85 c average ambient temperature 2 2 ambient temperature averaged over duration of applic ation, not to exceed recommended product operating temperature range. blocks with 0?1,000 p/e cycles 20 ? years blocks with 10,000 p/e cycles 10 ? years blocks with 100,000 p/e cycles 1?5 (1) ?years table 25. flash read access timing symbol c parameter conditions 1 1 v dd = 3.3 v 10% / 5.0 v 10%, t a = ? 40 to 125 c, unless otherwise specified max unit f read cc p maximum frequency for flas h reading 2 wait states 64 mhz c 1 wait state 40 c 0 wait states 20 table 26. flash power supply dc electrical characteristics symbol c parameter conditions 1 value 2 unit min typ max i fread cc d sum of the current consumption on v ddhv and v ddbv on read access flash module read f cpu = 64 mhz 3 33 ma i fmod cc d sum of the current consumption on v ddhv and v ddbv on matrix modification (program/erase) program/erase on-going while reading flash registers f cpu = 64 mhz (3) 33 ma i flpw cc d sum of the current consumption on v ddhv and v ddbv during flash low-power mode 900 a MPC5604B/c microcontrolle r data sheet, rev. 2 preliminary?subject to change without notice freescale semiconductor 31 4.11.3 start-up/switch-off timings 4.12 electromagnetic compatib ility (emc) characteristics susceptibility tests are performed on a sa mple basis during produ ct characterization. 4.12.1 designing hardened software to avoid noise problems emc characterization and optimiza tion are performed at component level with a typical application environment and simplified mcu software. it should be noted that good emc performance is highly dependent on the user application and the software in particular. therefore it is recommended that the user apply emc software optimization and pre-qualification tests in relation with the emc level requested for his application. ? software recommendations ? the software flowchart must include the ma nagement of runaway conditions such as: ? corrupted program counter ? unexpected reset ? critical data corruption (control registers...) ? prequalification trials ? most of the common failures (unexpected re set and program counter corruption) can be reproduced by manually forcing a low state on the reset pin or the oscillator pins for 1 second. i fpwd cc d sum of the current consumption on v ddhv and v ddbv during flash power-down mode 150 a 1 v dd = 3.3 v 10% / 5.0 v 10%, t a = ? 40 to 125 c, unless otherwise specified 2 all values need to be confirmed during device validation. 3 f cpu 64 mhz can be achieved only at up to 105 c table 27. start-up time/switch-off time symbol c parameter conditions 1 1 v dd = 3.3 v 10% / 5.0 v 10%, t a = ? 40 to 125 c, unless otherwise specified value unit min typ max t flarstexit cc t delay for flash module to exit reset mode 125 s t flalpexit cc t delay for flash module to exit low-power mode 0.5 t flapdexit cc t delay for flash module to exit power-down mode 30 t flalpentry cc t delay for flash module to enter low-power mode 0.5 t flapdentry cc t delay for flash module to enter power-down mode 1.5 table 26. flash power supply dc electrical characteristics symbol c parameter conditions 1 value 2 unit min typ max MPC5604B/c microcontrolle r data sheet, rev. 2 preliminary?subject to change without notice freescale semiconductor 32 to complete these trials, esd stress can be applied directly on the device. when unexpected behavior is detected, the software can be hardened to prev ent unrecoverable errors occurring. 4.12.2 electromagnetic interference (emi) the product is monitored in terms of emission based on a typical application. this emission test conforms to the iec 61967-1 standard, which specifies the general conditions for emi measurements. 4.12.3 absolute maximum ratings (electrical sensitivity) based on two different tests (esd and lu) using specific measurement me thods, the product is stressed in order to determine its performance in terms of electrical sensitivity. 4.12.3.1 electrostatic discharge (esd) electrostatic discharges (a positive then a negative pulse separated by 1 second) ar e applied to the pins of each sample accord ing to each pin combination. the sample size de pends on the number of suppl y pins in the device (3 pa rts*(n+1) suppl y pin). this test conforms to the aec- q100-002/-003/-011 standard. table 28. emi radiated emission measurement 1,2 1 emi testing and i/o port waveforms per iec 61967-1, -2, -4 2 for information on conducted emission and susceptibility measurement (norm iec 61967-4), please contact your local marketing representative. symbol c parameter conditions value unit min typ max ? sr ? scan range 0.150 1000 mhz f cpu sr ? operating frequency 64 mhz v dd_lv sr ? lv operating voltages 1.28 v s emi cc t peak level v dd = 5v, t a =25c, lqfp144 package test conforming to iec 61967-2, f osc = 8 mhz/f cpu = 64 mhz no pll frequency modulation 18 dbv 2% pll frequency modulation 14 3 3 all values need to be confirmed during device validation dbv table 29. esd absolute maximum ratings 1 2 1 all esd testing is in conformity with cdf-aec-q100 stre ss test qualification for au tomotive grade integrated circuits. symbol c ratings conditions class max value unit v esd(hbm) cc t electrostatic discharge voltage (human body model) t a = 25 c conforming to aec-q100-002 h1c 2000 v v esd(mm) cc t electrostatic discharge voltage (machine model) t a = 25 c conforming to aec-q100-003 m2 200 v esd(cdm) cc t electrostatic discharge voltage (charged device model) t a = 25 c conforming to aec-q100-011 c3a 500 750 (corners) MPC5604B/c microcontrolle r data sheet, rev. 2 preliminary?subject to change without notice freescale semiconductor 33 4.12.3.2 static latch-up (lu) two complementary static tests are required on six parts to assess the latch-up performance: ? a supply overvoltage is appl ied to each power supply pin. ? a current injection is applied to each input, output and configurable i/o pin. these tests are compliant with the eia/jesd 78 ic latch-up standard. 4.13 fast external crystal oscill ator (4 to 16 mhz) electrical characteristics the device provides an oscillator/resonator driver. figure 10 describes a simple model of the internal oscillat or driver and provides an example of a connection for an oscillator or a resonator. table 31 provides the parameter description of 4 mhz to 16 mhz crystals used for the design simulations. figure 10. crystal oscillator and resonator connection scheme 2 a device will be defined as a failure if after exposure to esd pulses the device no longer meets the device specification requirements. complete dc parametric and f unctional testing shall be performed per applicable device specification at room temperature followed by ho t temperature, unless specified otherwise in the device specification. table 30. latch-up results symbol c parameter conditions class lu cc t static latch-up class t a = 125 c conforming to jesd 78 ii level a c2 c1 crystal xtal extal resonator xtal extal device device device xtal extal i r v dd MPC5604B/c microcontrolle r data sheet, rev. 2 preliminary?subject to change without notice freescale semiconductor 34 note xtal/extal must not be directly used to drive external circuits. figure 11. fast external crystal oscillator (4 to 16 mhz) electrical characteristics table 31. crystal description nominal frequency (mhz) ndk crystal reference crystal equivalent series resistance esr crystal motional capacitance (c m ) ff crystal motional inductance (l m ) mh load on xtalin/xtalout c1 = c2 (pf) 1 1 the values specified for c1 and c2 are the same as used in simulations. it should be ensured that the testing includes all the parasitics (from the board, probe, crystal, et c.) as the ac / transient behavior depends upon them. shunt capacitance between xtalout and xtalin c0 2 (pf) 2 the value of c0 specified here includes 2 pf additional capacitance for parasitics (to be seen with bond-pads, package, etc.). 4 nx8045gb 300 2.68 591.0 21 2.93 8 nx5032ga 300 2.46 160.7 17 3.01 10 150 2.93 86.6 15 2.91 12 120 3.11 56.5 15 2.93 16 120 3.90 25.3 10 3.00 table 32. fast external crystal oscillator (4 to 16 mhz) electrical characteristics symbol c parameter conditions 1 value 2 unit min typ max f fxosc sr ? fast external crystal oscillator frequency 4.0 16.0 mhz v fxoscop t fxoscsu v xtal v fxosc valid internal clock 90% 10% 1/f fxosc s_mtrans bit (me_gs register) ?1? ?0? MPC5604B/c microcontrolle r data sheet, rev. 2 preliminary?subject to change without notice freescale semiconductor 35 4.14 slow external crystal oscillator (32 khz) electrical characteristics the device provides a low power oscillator/resonator driver. g mfxosc cc c fast external crystal oscillator transconductance v dd = 3.3 v 10%, pad3v5v = 1 oscillator_margin = 0 2.2 8.2 ma/v cc p v dd = 5.0 v 10%, pad3v5v = 0 oscillator_margin = 0 2.0 7.4 cc c v dd = 3.3 v 10%, pad3v5v = 1 oscillator_margin = 1 2.7 9.7 cc c v dd = 5.0 v 10%, pad3v5v = 0 oscillator_margin = 1 2.5 9.2 v fxosc cc t oscillation amplitude at extal f osc = 4 mhz, oscillator_margin = 0 1.3 v f osc = 16 mhz, oscillator_margin = 1 1.3 v fxoscop cc p oscillation operating point 0.95 v i fxosc ,3 cc t fast external crystal oscillator consumption 3ma t fxoscsu cc t fast external crystal oscillator start-up time f osc = 4 mhz, oscillator_margin = 0 6ms f osc = 16 mhz, oscillator_margin = 1 1.8 v ih sr p input high level cmos (schmitt trigger) oscillator bypass mode 0.65v dd v dd +0.4 v v il sr p input low level cmos (schmitt trigger) oscillator bypass mode ? 0.4 0.35v dd v 1 v dd = 3.3 v 10% / 5.0 v 10%, t a = ? 40 to 125 c, unless otherwise specified 2 all values need to be confirmed during device validation. 3 stated values take into account only analog module cons umption but not the digital contributor (clock tree and enabled peripherals) table 32. fast external crystal oscillator (4 to 16 mhz) electrical characteristics (continued) symbol c parameter conditions 1 value 2 unit min typ max MPC5604B/c microcontrolle r data sheet, rev. 2 preliminary?subject to change without notice freescale semiconductor 36 figure 12. crystal oscillator and resonator connection scheme note osc32k_xtal/osc32k_extal must not be dir ectly used to drive external circuits. figure 13. equivalent circuit of a quartz crystal table 33. crystal motional characteristics 1 1 the crystal used is epson toyocom mc306. symbol parameter conditions value unit min typ max l m motional inductance ? 11.796 kh c m motional capacitance ? 2 ff c1/c2 load capacitance at osc32k_xtal and osc32k_extal with respect to ground 2 18 28 pf r m 3 motional resistance ac coupled @ c0 = 2.85 pf 4 65 kw ac coupled @ c0 = 4.9 pf (4) 50 ac coupled @ c0 = 7.0 pf (4) 35 ac coupled @ c0 = 9.0 pf (4) 30 osc32k_xtal osc32k_extal device c2 c1 crystal osc32k_xtal osc32k_extal resonator device c0 c2 c1 c2 r m c1 l m c m crystal MPC5604B/c microcontrolle r data sheet, rev. 2 preliminary?subject to change without notice freescale semiconductor 37 figure 14. slow external crystal oscillator (32 khz) electrical characteristics 2 this is the recommended range of load capacitance at osc32k_xtal and osc32k_extal with respect to ground. it includes all the parasitics due to board traces, crystal and package. 3 maximum esr (r m ) of the crystal is 50 k 4 c0 includes a parasitic capacitance of 2.0 pf between osc32k_xtal and osc32k_extal pins table 34. slow external crystal oscillator (32 khz) electrical characteristics symbol c parameter conditions 1 1 v dd = 3.3 v 10% / 5.0 v 10%, t a = ? 40 to 125 c, unless otherwise specified value 2 2 all values need to be confirmed during device validation. unit min typ max f sxosc sr ? slow external crystal oscillator frequency 32 32.768 40 khz g msxosc cc ? slow external crystal oscillator transconductance v dd = 3.3 v 10%, pad3v5v = 1 tbd ma/v v dd = 5.0 v 10% pad3v5v = 0 tbd v dd = 3.3 v 10%, pad3v5v = 1 tbd v dd = 5.0 v 10%, pad3v5v = 0 tbd v sxosc cc t oscillation amplitude 0.6 v i sxoscbias cc t oscillation bias current tbd a i sxosc cc t slow external crystal oscillator consumption 8a t sxoscsu cc t slow external crystal oscillator start-up time 2s oscon bit (osc_ctl register) t sxoscsu 1 v osc32k_xtal v sxosc valid internal clock 90% 10% 1/f sxosc 0 MPC5604B/c microcontrolle r data sheet, rev. 2 preliminary?subject to change without notice freescale semiconductor 38 4.15 fmpll electrical characteristics the device provides a frequency-modulated phase-locked loop (fmp ll) module to generate a fast system clock from the main oscillator driver. 4.16 fast internal rc oscillator (16 mhz) electrical characteristics the device provides a 16 mhz fast internal rc oscillator. this is used as the default clock at the power-up of the device. table 35. fmpll electrical characteristics symbol c parameter conditions 1 1 v dd = 3.3 v 10% / 5.0 v 10%, t a = ? 40 to 125 c, unless otherwise specified. value 2 2 all values need to be confirmed during device validation. unit min typ max f pllin sr ? fmpll reference clock 3 3 pllin clock retrieved directly from fxosc clock. input characteristics are granted when oscillator is used in functional mode. when bypass mode is used, oscillator input clock should verify f pllin and pllin . 464mhz pllin sr ? fmpll reference clock duty cycle (3) 40 60 % f pllout cc p fmpll output clock frequency 16 64 mhz f cpu sr ? system clock frequency 64 4 4 f cpu 64 mhz can be achieved only at up to 105 c mhz f free cc p free-running frequency 20 150 mhz t lock cc p fmpll lock time stable oscillator (f pllin = 16 mhz) 40 100 s t ltjit cc ? fmpll long term jitter f pllin = 16 mhz (resonator) , f pllclk @ 64 mhz, 4000 cycles tbd ns i pll cc c fmpll consumption t a = 25 c 4 ma table 36. fast internal rc oscillator (16 mhz) electrical characteristics symbol c parameter conditions 1 value 2 unit min typ max f firc cc p fast internal rc oscillator high frequency t a = 25 c, trimmed 16 mhz sr ? 12 20 i fircrun 3, cc t fast internal rc oscillator high frequency current in running mode t a = 25 c, trimmed 200 a i fircpwd cc d fast internal rc oscillator high frequency current in power down mode t a = 25 c tbd 10 a ?t a = 55 c tbd tbd MPC5604B/c microcontrolle r data sheet, rev. 2 preliminary?subject to change without notice freescale semiconductor 39 4.17 slow internal rc oscillator (128 khz) electrical characteristics the device provides a 128 khz slow internal rc oscillator. this can be used as the reference clock for the rtc module. i fircstop cc t fast internal rc oscillator high frequency and system clock current in stop mode t a = 25 c sysclk = off 500 a sysclk = 2 mhz 600 sysclk = 4 mhz 700 sysclk = 8 mhz 900 sysclk = 16 mhz 1250 t fircsu cc c fast internal rc oscillator start-up time t a = 55 c v dd = 5.0 v 10% 1.1 2.0 s ?v dd = 3.3 v 10% tbd tbd ?t a = 125 c v dd = 5.0 v 10% tbd ?v dd = 3.3 v 10% tbd fircpre cc c fast internal rc oscillator precision after software trimming of f firc t a = 25 c ? 1+1% firctrim cc c fast internal rc oscillator trimming step t a = 25 c 1.6 % fircvar cc c fast internal rc oscillator variation in temperature and supply with respect to f firc at t a = 55 c in high-frequency configuration ? 5+5% 1 v dd = 3.3 v 10% / 5.0 v 10%, t a = ? 40 to 125 c, unless otherwise specified. 2 all values need to be confirmed during device validation. 3 this does not include consumption linked to clock tree toggling and peripherals consumption when rc oscillator is on. table 37. slow internal rc oscillator (128 khz) electrical characteristics symbol c parameter conditions 1 value 2 unit min typ max f sirc cc p slow internal rc oscillator low frequency t a = 25 c, trimmed 128 khz sr ? 100 150 i sirc 3, cc c slow internal rc oscillator low frequency current t a = 25 c, trimmed 5 a t sircsu cc p slow internal rc oscillator start-up time t a = 25 c, v dd = 5.0 v 10% tbd 8 12 s table 36. fast internal rc oscillator (16 mhz) electrical characteristics (continued) symbol c parameter conditions 1 value 2 unit min typ max MPC5604B/c microcontrolle r data sheet, rev. 2 preliminary?subject to change without notice freescale semiconductor 40 4.18 on-chip peripherals 4.18.1 current consumption sircpre cc c slow internal rc oscillator precision after software trimming of f sirc t a = 25 c ? 2+2% sirctrim cc c slow internal rc oscillator trimming step 2.7 sircvar cc c slow internal rc oscillator variation in temperature and supply with respect to f sirc at t a = 55 c in high frequency configuration high frequency configuration ? 10 +10 % 1 v dd = 3.3 v 10% / 5.0 v 10%, t a = ? 40 to 125 c, unless otherwise specified. 2 all values need to be confirmed during device validation. 3 this does not include consumption linked to clock tree toggling and peripherals consumption when rc oscillator is on. table 38. on-chip peripherals current consumption symbol c parameter conditions value unit min typ max i dd(adc) cc t adc supply current t a =25c tbd a/mhz i dd(can) cc t can (flexcan) supply current t a =25c tbd i dd(ctu) cc t ctu supply current t a =25c tbd i dd(emios) cc t emios supply current t a =25c tbd i dd(flash) cc t flash supply current (see ta b l e 2 6 ) i dd(i2c) cc t i2c supply current t a =25c tbd a/mhz i dd(fmpll) cc t fmpll supply current (see ta b l e 3 5 ) i dd(rtc) cc t rtc supply current t a =25c tbd a/mhz i dd(sci) cc t sci (linflex) supply current t a =25c tbd i dd(siu) cc t siu supply current t a =25c tbd i dd(spi) cc t spi (dspi) supply current t a =25c tbd i dd(swt) cc t swt supply current t a =25c tbd table 37. slow internal rc oscillator (128 khz) electrical characteristics (continued) symbol c parameter conditions 1 value 2 unit min typ max MPC5604B/c microcontrolle r data sheet, rev. 2 preliminary?subject to change without notice freescale semiconductor 41 4.18.2 dspi characteristics table 39. dspi characteristics no. symbol c parameter value unit min typ max 1t sck sr d sck cycle time 64 ns ?f dspi sr d dspi digital controller frequency f cpu mhz ? t csc cc d internal delay between pad associated to sck and pad associated to csn in master mode 120 1 1 maximum is reached when csn pad is configured as sl ow pad while sck pad is configured as medium pad. ns 2t cscext 2 2 the t csc delay value is configurable through a register. when configuring t csc (using pcssck and cssck fields in dspi_ctarx registers), delay between internal cs and internal sck must be higher than t csc to ensure positive t cscext . cc d cs to sck delay master mode t cscext = t csc + t csc ns sr d slave mode 32 3t ascext 3 3 the t asc delay value is configurable through a register. when configuring t asc (using pasc and asc fields in dspi_ctarx registers), delay between internal cs and internal sck must be higher than t asc to ensure positive t ascext . cc d after sck delay master mode t ascext = t asc + t csc ns sr d slave mode 1/f dspi + 5 ns ns 4t sdc cc d sck duty cycle master mode t sck /2 ns sr d slave mode t sck /2 5t a sr d slave access time 27 ns 6t di sr d slave sout disable time 0 ns 7? 8? 9t sui sr d data setup time for inputs master (mtfe = 0) 35 ns slave 5 master (mtfe = 1) 35 10 t hi sr d data hold time for inputs master (mtfe = 0) 0 ns slave 2 4 4 this delay value corresponds to smpl_pt = 00b which is bit field 9 and 8 of dspi_mcr register. master (mtfe = 1) 0 11 t suo 5 5 sck and sout configured as medium pad cc d data valid after sck edge master (mtfe = 0) 32 ns slave 34 master (mtfe = 1) 32 12 t ho (5) cc d data hold time for outputs master (mtfe = 0) 2 ns slave 5.5 master (mtfe = 1) 2 MPC5604B/c microcontrolle r data sheet, rev. 2 preliminary?subject to change without notice freescale semiconductor 42 figure 15. dspi classic spi timing ? master, cpha = 0 figure 16. dspi classic spi timing ? master, cpha = 1 data last data first data first data data last data sin sout pcsx sck output 4 9 12 1 11 10 4 sck output (cpol = 0) (cpol = 1) 3 2 note: numbers shown reference ta b l e 3 9 . data last data first data sin sout 12 11 10 last data data first data sck output sck output pcsx 9 (cpol = 0) (cpol = 1) note: numbers shown reference ta bl e 3 9 . MPC5604B/c microcontrolle r data sheet, rev. 2 preliminary?subject to change without notice freescale semiconductor 43 figure 17. dspi classic spi timing ? slave, cpha = 0 figure 18. dspi classic spi timing ? slave, cpha = 1 last data first data 3 4 1 data data sin sout ss 4 5 6 9 11 10 12 sck input first data last data sck input 2 (cpol = 0) (cpol = 1) note: numbers shown reference ta bl e 3 9 . 5 6 9 12 11 10 last data last data sin sout ss first data first data data data sck input sck input (cpol = 0) (cpol = 1) note: numbers shown reference ta bl e 3 9 . MPC5604B/c microcontrolle r data sheet, rev. 2 preliminary?subject to change without notice freescale semiconductor 44 figure 19. dspi modified transfer format timing ? master, cpha = 0 figure 20. dspi modified transfer format timing ? master, cpha = 1 pcsx 3 1 4 10 4 9 12 11 sck output sck output sin sout first data data last data first data data last data 2 (cpol = 0) (cpol = 1) note: numbers shown reference ta bl e 3 9 . pcsx 10 9 12 11 sck output sck output sin sout first data data last data first data data last data (cpol = 0) (cpol = 1) note: numbers shown reference ta bl e 3 9 . MPC5604B/c microcontrolle r data sheet, rev. 2 preliminary?subject to change without notice freescale semiconductor 45 figure 21. dspi modified transfer format timing ? slave, cpha = 0 figure 22. dspi modified transfer format timing ? slave, cpha = 1 last data first data 3 4 1 data data sin sout ss 4 5 6 9 11 10 sck input first data last data sck input 2 (cpol = 0) (cpol = 1) 12 note: numbers shown reference ta b l e 3 9 . 5 6 9 12 11 10 last data last data sin sout ss first data first data data data sck input sck input (cpol = 0) (cpol = 1) note: numbers shown reference ta bl e 3 9 . MPC5604B/c microcontrolle r data sheet, rev. 2 preliminary?subject to change without notice freescale semiconductor 46 figure 23. dspi pcs strobe (pcss ) timing 4.18.3 nexus characteristics table 40. nexus characteristics no. symbol c parameter value unit min typ max 1t tcyc cc d tck cycle time 64 ns 2t mcyc cc d mcko cycle time 32 ns 3t mdov cc d mcko low to mdo data valid 8 ns 4t mseov cc d mcko low to mseo_b data valid 8 ns 5t evtov cc d mcko low to evto data valid 8 ns 10 t ntdis cc d tdi data setup time 15 ns t ntmss cc d tms data setup time 15 ns 11 t ntdih cc d tdi data hold time 5 ns t ntmsh cc d tms data hold time 5 ns 12 t tdov cc d tck low to tdo data valid 35 ns 13 t tdoi cc d tck low to tdo data invalid 6 ns pcsx 7 8 pcss note: numbers shown reference ta bl e 3 9 . MPC5604B/c microcontrolle r data sheet, rev. 2 preliminary?subject to change without notice freescale semiconductor 47 figure 24. nexus tdi, tms, tdo timing 4.18.4 jtag characteristics table 41. jtag characteristics no. symbol c parameter value unit min typ max 1t jcyc cc d tck cycle time 64 ns 2t tdis cc d tdi setup time 15 ns 3t tdih cc d tdi hold time 5 ns 4t tmss cc d tms setup time 15 ns 5t tmsh cc d tms hold time 5 ns 6t tdov cc d tck low to tdo valid 33 ns 7t tdoi cc d tck low to tdo invalid 6 ns 10 tck tms, tdi tdo 11 12 note: numbers shown reference ta bl e 4 0 . MPC5604B/c microcontrolle r data sheet, rev. 2 preliminary?subject to change without notice freescale semiconductor 48 figure 25. timing diagram ? jtag boundary scan input data valid output data valid data inputs data outputs data outputs tck note: numbers shown reference ta bl e 4 1 . 3/5 2/4 7 6 MPC5604B/c microcontrolle r data sheet, rev. 2 preliminary?subject to change without notice freescale semiconductor 49 4.18.5 adc electrical characteristics 4.18.5.1 introduction the device provides a 10-bit successive approxima tion register (sar) analog-to-digital converter. figure 26. adc characteristic and error definitions 4.18.5.2 input impedance and adc accuracy in the following analysis, the input circuit corres ponding to the precise ch annels is considered. to preserve the accuracy of the a/d converter, it is necessary that analog input pins have low ac impedance. placing a capacito r with good high frequency characteristics at the input pin of th e device can be effective: the capacitor should be as large as possible, ideally infinite. this capacitor contributes to attenuat ing the noise present on the input pin; furthermore, it sourc es charge during the sampling phase, when the anal og signal source is a high-impedance source. (2) (1) (3) (4) (5) offset error ose offset error ose gain error ge 1 lsb (ideal) v in(a) (lsb ideal ) (1) example of an actual transfer curve (2) the ideal transfer curve (3) differential non-linearity error (dnl) (4) integral non-linearity error (inl) (5) center of a step of the actual transfer curve code out 1023 1022 1021 1020 1019 1018 5 4 3 2 1 0 7 6 1 2 3 4 5 6 7 1017 1018 1019 1020 1021 1022 1023 1 lsb ideal = v dd_adc / 1024 MPC5604B/c microcontrolle r data sheet, rev. 2 preliminary?subject to change without notice freescale semiconductor 50 a real filter can typically be obtained by using a series re sistance with a capacitor on the input pin (simple rc filter). the rc filtering may be limited according to the value of source impedance of the tr ansducer or circuit supp lying the analog signal to be measured. the filter at the input pins mu st be designed taking into account the d ynamic characteristics of the input signal (bandwidth) and the equivalent input impedance of the adc itself. in fact a current sink contri butor is represented by the charge shari ng effects with the sampling capacitance: c s being substantially a switched capacitance, with a frequency equal to the conversion rate of the adc, it can be seen as a resistive p ath to ground. for instance, assuming a conversion rate of 1 mhz, with c s equal to 3 pf, a resistance of 330 k is obtained (r eq = 1 / (f c *c s ), where f c represents the conversion rate at the considered channel). to minimize the error indu ced by the voltage partitioning between this resistance (sampled voltage on c s ) and the sum of r s + r f + r l + r sw + r ad , the external circuit must be designed to respect the equation 4 : eqn. 4 equation 4 generates a constraint for external network design, in pa rticular on a resistive path. internal switch resistances (r sw and r ad ) can be neglected with respect to external resistances. figure 27. input equivalent circui t (precise channels) v a r s r f r l r sw r ad +++ + r eq --------------------------------------------------------------------------- ? 1 2 -- -lsb < r s source impedance r f filter resistance c f filter capacitance r l current limiter resistance r sw1 channel selection switch impedance r ad sampling switch impedance c p pin capacitance (two contributions, c p1 and c p2 ) c s sampling capacitance c p1 r ad channel selection v a MPC5604B/c microcontrolle r data sheet, rev. 2 preliminary?subject to change without notice freescale semiconductor 51 figure 28. input equivalent circuit (extended channels) a second aspect involving the capacitance network sha ll be considered. assuming the three capacitances c f , c p1 and c p2 are initially charged at the source voltage v a (refer to the equivalent circuit in figure 27 ): a charge sharing phenomenon is installed when the sampling phase is st arted (a/d switch close). figure 29. transient behavior during sampling phase in particular two different transient periods can be distinguished: 1. a first and quick charge transfer from the internal capacitance c p1 and c p2 to the sampling capacitance c s occurs (c s is supposed initially completely di scharged): considering a worst case (since the time constant in real ity would be faster) in which c p2 is reported in parallel to c p1 (call c p = c p1 + c p2 ), the two capacitances c p and c s are in series, and the time constant is r f c f r s r l r sw1 c p3 c s v dd sampling source filter current limiter external circuit internal circuit scheme r s source impedance r f filter resistance c f filter capacitance r l current limiter resistance r sw channel selection switch impedance (two contributions r sw1 and r sw2 ) r ad sampling switch impedance c p pin capacitance (three contributions, c p1 , c p2 and c p3 ) c s sampling capacitance c p1 r ad channel selection v a c p2 extended r sw2 switch v a v a1 v a2 t t s v cs voltage transient on c s v < 0.5 lsb 1 2 1 < (r sw + r ad ) c s << t s 2 = r l (c s + c p1 + c p2 ) MPC5604B/c microcontrolle r data sheet, rev. 2 preliminary?subject to change without notice freescale semiconductor 52 eqn. 5 equation 5 can again be simplifi ed considering only c s as an additional worst condition. in reality, the transient is faster, but the a/d converter circuitry has been designed to be robust also in the very worst case: the sampling time t s is always much longer than the internal time constant: eqn. 6 the charge of c p1 and c p2 is redistributed also on c s , determining a new value of the voltage v a1 on the capacitance according to equation 7 : eqn. 7 2. a second charge transfer involves also c f (that is typically bigger th an the on-chip capacitance) through the resistance r l : again considering the worst case in which c p2 and c s were in parallel to c p1 (since the time constant in reality w ould be faster), the time constant is: eqn. 8 in this case, the time constant depends on the external circuit: in particular imposing that the transient is completed well before the end of sampling time t s , a constraints on r l sizing is obtained: eqn. 9 of course, r l shall be sized also according to the current limitation constr aints, in combination with r s (source impedance) and r f (filter resistance). being c f definitively bigger than c p1 , c p2 and c s , then the final voltage v a2 (at the end of the charge transfer tr ansient) will be mu ch higher than v a1 . equation 10 must be respected (charge balance assuming now c s already charged at v a1 ): eqn. 10 the two transients above are not influenced by th e voltage source that, due to the presence of the r f c f filter, is not able to provide the extra charge to comp ensate the voltage drop on c s with respect to the ideal source v a ; the time constant r f c f of the filter is very high with respect to the sampling time (t s ). the filter is ty pically designed to act as anti-aliasing. 1 r sw r ad + () = c p c s ? c p c s + --------------------- ? 1 r sw r ad + () < c s t s ? ? () ? v a c p1 c p2 + () ? = 2 r l < c s c p1 c p2 ++ () ? 2 ? 10 r l c s c p1 c p2 ++ () ? ? =t s < () ? v a c f ? v a1 +c p1 c p2 +c s + () ? = MPC5604B/c microcontrolle r data sheet, rev. 2 preliminary?subject to change without notice freescale semiconductor 53 figure 30. spectral representation of input signal calling f 0 the bandwidth of the source signal (and as a conseque nce the cut-off frequency of the anti-aliasing filter, f f ), according to the nyquist theorem the conversion rate f c must be at least 2f 0 ; it means that the constant ti me of the filter is greater than or at least equal to twice the conversion period (t c ). again the conversion period t c is longer than the sampling time t s , which is just a portion of it, even when fixed channel continu ous conversion mode is selected (fastest conversion rate at a specific channel): in conclusion it is evident that the time constant of the filter r f c f is definitively much higher than the sampling time t s , so the charge level on c s cannot be modified by the analog signal source during the time in which the sampling switch is closed. the considerations above lead to impose new constraints on the external circuit, to reduce the accur acy error due to the voltag e drop on c s ; from the two charge balance equations above, it is simple to derive equation 11 between the ideal and real sampled voltage on c s : eqn. 11 from this formula, in the worst case (when v a is maximum, that is for instance 5 v ), assuming to accept a maximum error of half a count, a constraint is evident on c f value: eqn. 12 f 0 f analog source bandwidth (v a ) f 0 f sampled signal spectrum (f c = conversion rate) f c f anti-aliasing filter (f f = rc filter pole) f f 2 f 0 < f c (nyquist) f f = f 0 (anti-aliasing filtering condition) t c < 2 r f c f (conversion rate vs. filter pole) noise v a v a2 ----------- - c p1 c p2 +c f + c p1 c p2 +c f c s ++ ------------------------------------------------------- - = c f 2048 c s ? > MPC5604B/c microcontrolle r data sheet, rev. 2 preliminary?subject to change without notice freescale semiconductor 54 4.18.5.3 adc electrical characteristics table 42. adc input leakage current symbol c parameter conditions value unit min typ max i lkg cc c input leakage current t a = ? 40 c no current injection on adjacent pin 1 na ct a = 25 c 1 ct a = 105 c 8 200 pt a = 125 c 45 400 table 43. adc conversion characteristics symbol c parameter conditions 1 value unit min typ max v ss_adc sr ? voltage on vss_hv_adc (adc reference) pin with respect to ground (v ss ) 2 ? 0.1 0.1 v v dd_adc sr ? voltage on vdd_hv_adc pin (adc reference) with respect to ground (v ss ) v dd ? 0.1 v dd +0.1 v v ainx sr ? analog input voltage 3 v ss_adc ? 0.1 v dd_adc +0.1 v f adc sr ? adc analog frequency 6 32 + 4% mhz adc_sys sr ? adc digital clock duty cycle (ipg_clk) adclksel = 1 4 45 55 % t adc_pu sr ? adc power up delay 1.5 s t adc_s cc t sample time 5 f adc = 32 mhz, adc_conf_sample_input = 17 0.5 s f adc = 6 mhz, inpsamp = 255 42 t adc_c cc p conversion time 6 f adc = 32 mhz, adc_conf_comp = 2 0.625 s c s cc d adc input sampling capacitance 3 pf c p1 cc d adc input pin capacitance 1 3 pf c p2 cc d adc input pin capacitance 2 1 pf c p3 cc d adc input pin capacitance 3 1 pf MPC5604B/c microcontrolle r data sheet, rev. 2 preliminary?subject to change without notice freescale semiconductor 55 r sw1 cc d internal resistance of analog source 3 k r sw2 cc d internal resistance of analog source 2 k r ad cc d internal resistance of analog source 0.1 k i inj sr ? input current injection current injection on one adc input, different from the converted one v dd = 3.3 v 10% ? 5 5 ma v dd = 5.0 v 10% ? 5 5 | inl | cc t absolute value for integral non-linearity no overload 0.5 1.5 lsb | dnl | cc t absolute differential non-linearity no overload 0.5 1.0 lsb | ofs | cc t absolute offset error 0.5 lsb | gne | cc t absolute gain error 0.6 lsb tuep cc p total unadjusted error 7 for precise channels, input only pins without current injection ? 2 0.6 2 lsb t with current injection ? 3 3 tuex cc t total unadjusted error (7) for extended channel without current injection ? 3 1 3 lsb t with current injection ? 4 4 1 v dd = 3.3 v 10% / 5.0 v 10%, t a = ? 40 to 125 c, unless otherwise specified. 2 analog and digital v ss must be common (to be tied together externally). 3 v ainx may exceed v ss_adc and v dd_adc limits, remaining on absolute maximu m ratings, but the results of the conversion will be clamped respectively to 0x000 or 0x3ff. 4 duty cycle is ensured by using system clock without prescaling. when adclksel = 0, th e duty cycle is ensured by internal divider by 2. 5 during the sample time the input capacitance c s can be charged/discharged by the external source. the internal resistance of the analog source must allow the c apacitance to reach its final voltage level within t adc_s . after the end of the sample time t adc_s , changes of the analog input voltage have no effect on the conversion result. values for the sample clock t adc_s depend on programming. 6 this parameter does not include the sample time t adc_s , but only the time for determining the digital result and the time to load the result?s register with the conversion result. 7 total unadjusted error: the maximum error that occurs wit hout adjusting offset and gain errors. this error is a combination of offset, gain and integral linearity errors. table 43. adc conversion characteristics (continued) symbol c parameter conditions 1 value unit min typ max MPC5604B/c microcontrolle r data sheet, rev. 2 preliminary?subject to change without notice freescale semiconductor 56 5 package characteristics 5.1 package mechanical data figure 31. 144 lqfp package mechanical drawing (1 of 2) MPC5604B/c microcontrolle r data sheet, rev. 2 preliminary?subject to change without notice freescale semiconductor 57 figure 32. 144 lqfp package mechanical drawing (2 of 2) MPC5604B/c microcontrolle r data sheet, rev. 2 preliminary?subject to change without notice freescale semiconductor 58 figure 33. 100 lqfp package mechanical drawing (1 of 4) MPC5604B/c microcontrolle r data sheet, rev. 2 preliminary?subject to change without notice freescale semiconductor 59 figure 34. 100 lqfp package mechanical drawing (2 of 4) MPC5604B/c microcontrolle r data sheet, rev. 2 preliminary?subject to change without notice freescale semiconductor 60 figure 35. 100 lqfp package mechanical drawing (3 of 4) MPC5604B/c microcontrolle r data sheet, rev. 2 preliminary?subject to change without notice freescale semiconductor 61 figure 36. 100 lqfp package mechanical drawing (4 of 4) MPC5604B/c microcontrolle r data sheet, rev. 2 preliminary?subject to change without notice freescale semiconductor 62 figure 37. 208 mapbga package mechanical drawing (1 of 2) MPC5604B/c microcontrolle r data sheet, rev. 2 preliminary?subject to change without notice freescale semiconductor 63 figure 38. 208 mapbga package mechanical drawing (2 of 2) MPC5604B/c microcontrolle r data sheet, rev. 2 preliminary?subject to change without notice freescale semiconductor 64 6 ordering information table 44. orderable part number summary orderable part number cpu code flash / sram (kbytes) package operating temp. (c) speed (mhz) data flash voltage packing mpc5602bemll e200z0h 256 / 24 100 lqfp ? 40 to 125 60 4 x 16 kb 3.3/5 v tray mpc5602bemllr tape & reel mpc5602bemlq e200z0h 256 / 24 144 lqfp ? 40 to 125 60 4 x 16 kb 3.3/5 v tray mpc5602bemlqr tape & reel mpc5602cemll e200z0h 256 / 32 100 lqfp ? 40 to 125 60 4 x 16 kb 3.3/5 v tray mpc5602cemllr tape & reel mpc5603bemll e200z0h 384 / 28 100 lqfp ? 40 to 125 60 4 x 16 kb 3.3/5 v tray mpc5603bemllr tape & reel mpc5603bemlq e200z0h 384 / 28 144 lqfp ? 40 to 125 60 4 x 16 kb 3.3/5 v tray mpc5603bemlqr tape & reel mpc5603cemll e200z0h 384 / 40 100 lqfp ? 40 to 125 60 4 x 16 kb 3.3/5 v tray mpc5603cemllr tape & reel mpc5602bevll e200z0h 256 / 24 100 lqfp ? 40 to 105 64 4 x 16 kb 3.3/5 v tray mpc5602bevllr tape & reel mpc5602bevlq e200z0h 256 / 24 144 lqfp ? 40 to 105 64 4 x 16 kb 3.3/5 v tray mpc5602bevlqr tape & reel mpc5602cevll e200z0h 256 / 32 100 lqfp ? 40 to 105 64 4 x 16 kb 3.3/5 v tray mpc5602cevllr tape & reel mpc5603bevll e200z0h 384 / 28 100 lqfp ? 40 to 105 64 4 x 16 kb 3.3/5 v tray mpc5603bevllr tape & reel mpc5603bevlq e200z0h 384 / 28 144 lqfp ? 40 to 105 64 4 x 16 kb 3.3/5 v tray mpc5603bevlqr tape & reel mpc5603cevll e200z0h 384 / 40 100 lqfp ? 40 to 105 64 4 x 16 kb 3.3/5 v tray mpc5603cevllr tape & reel MPC5604Bemll e200z0h 512 / 32 100 lqfp ? 40 to 125 60 4 x 16 kb 3.3/5 v tray MPC5604Bemllr tape & reel MPC5604Bemlq e200z0h 512 / 32 144 lqfp ? 40 to 125 60 4 x 16 kb 3.3/5 v tray MPC5604Bemlqr tape & reel MPC5604Bevll e200z0h 512 / 32 100 lqfp ? 40 to 105 64 4 x 16 kb 3.3/5 v tray MPC5604Bevllr tape & reel MPC5604B/c microcontrolle r data sheet, rev. 2 preliminary?subject to change without notice freescale semiconductor 65 figure 39. commercial product code structure 1 208 mapbga available only as de velopment package for nexus2+ 7 document revision history table 45 summarizes revisions to this document. MPC5604Bevlq e200z0h 512 / 32 144 lqfp ? 40 to 105 64 4 x 16 kb 3.3/5 v tray MPC5604Bevlqr tape & reel mpc5604cemll e200z0h 512 / 48 100 lqfp ? 40 to 125 60 4 x 16 kb 3.3/5 v tray mpc5604cemllr tape & reel MPC5604Bemmg e200z0h 512 / 48 208 map bga 1 ? 40 to 125 64 4 x 16 kb 3.3/5 v tray 1 208 mapbga available only as development package for nexus2+ table 45. revision history revision date substantive changes 1 4-apr-2008 initial release table 44. orderable part number summary (continued) orderable part number cpu code flash / sram (kbytes) package operating temp. (c) speed (mhz) data flash voltage packing qualification status powerpc core automotive platform core version flash size (core dependent) product optional fields mpc56 bemll example code: 04 temperature spec. package code qualification status m = mc status s = auto qualified p = pc status automotive platform 56 = ppc in 90nm 57 = ppc in 65nm core version 0 = e200z0 flash size (z0 core) 2 = 256 kb 3 = 384 kb 4 = 512 kb product b = body c = gateway optional fields e = data flash (blank if none) r = tape & reel (blank if tray) r temperature spec. c = -40 to 85 c v = -40 to 105 c m = -40 to 125 c package code ll = 100 lqfp lq = 144 lqfp mg = 208 mapbga 1 MPC5604B/c microcontrolle r data sheet, rev. 2 preliminary?subject to change without notice freescale semiconductor 66 1.1 15-apr-2008 added the following information missing in rev. 1: ? table headings in the ?device summary? table ? heading for the 208 mapbga column in the ?system pin descriptions? and ?functional port pin descriptions? tables 2 06-mar-2009 made minor editing and formatting changes to improve readability harmonized oscillator naming throughout document features: ?replaced 32 kb with 48 kb as max sram size ?updated descripiton of intc ?changed max number of gpio pins from 121 to 123 updated section 1.1, ?introduction updated ta bl e 2 added section 2, ?device blocks section 3, ?package pinouts : removed signal descriptions (these are found in the device reference manual) updated figure 2 : ?replaced vpp with vss_hv on pin 18 ?added ma[1] as af3 for pc[10] (pin 28) ?added ma[0] as af2 for pc[3] (pin 116) ?changed description for pin 120 to ph[10] / gpio[122] / tms ?changed description for pin 127 to ph[9] / gpio[121] / tck ?replaced nmi[0] with nmi on pin 11 updated figure 3 : ?replaced vpp with vss_hv on pin 14 ?added ma[1] as af3 for pc[10] (pin 22) ?added ma[0] as af2 for pc[3] (pin 77) ?changed description for pin 81 to ph[10] / gpio[122] / tms ?changed description for pin 88 to ph[9] / gpio[121] / tck ?removed e1uc[19] from pin 76 ?replaced [11] with wkup[11] for pb[3] (pin 1) ?replaced nmi[0] with nmi on pin 7 updated figure 4 : ?changed description for ball b8 from tck to ph[9] ?changed description for ball b9 from tms to ph[10] ?updated descriptions for balls r9 and t9 added section 4.2, ?parameter classification and tagged parameters in tables where appropriate added section 4.3, ?nvusro register updated ta bl e 7 section 4.5, ?recommended operating conditions : added note on ram data retention to end of section updated ta bl e 8 and ta bl e 9 added section 4.6.1, ?package thermal characteristics updated section 4.6.2, ?power considerations updated figure 5 updated ta bl e 1 2 , ta b l e 1 3 , ta b l e 1 4 , ta b l e 1 5 and ta b l e 1 6 table 45. revision history (continued) revision date substantive changes MPC5604B/c microcontrolle r data sheet, rev. 2 preliminary?subject to change without notice freescale semiconductor 67 appendix a abbreviations table 40 lists abbreviations used but not defined elsewhere in this document. 2 06-mar-2009 updated ta bl e 1 2 , ta b l e 1 3 , ta b l e 1 4 , ta b l e 1 5 and ta b l e 1 6 added section 4.7.4, ?output pin transition times updated ta bl e 1 9 updated figure 6 updated ta bl e 2 0 section 4.9.1, ?voltage regulator electrical characteristics : amended description of lv _ p l l figure 8 : exchanged position of symbols c dec1 and c dec2 updated ta bl e 2 1 table 40. abbreviations abbreviation meaning cmos complementary metal?oxide?semiconductor cpha clock phase cpol clock polarity cs peripheral chip select evto event out led light emitting diode mcko message clock out mdo message data out mseo message start/end out mtfe modified timing format enable sck serial communications clock sout serial data out tbd to be defined tck test clock input tdi test data input tdo test data output tms test mode select table 45. revision history (continued) revision date substantive changes document number: MPC5604Bc rev. 2 3/2009 how to reach us: home page: www.freescale.com web support: http://www.freescale.com/support usa/europe or locations not listed: freescale semiconductor, inc. technical information center, el516 2100 east elliot road tempe, arizona 85284 1-800-521-6274 or +1-480-768-2130 www.freescale.com/support europe, middle east, and africa: freescale halbleiter deutschland gmbh technical information center schatzbogen 7 81829 muenchen, germany +44 1296 380 456 (english) +46 8 52200080 (english) +49 89 92103 559 (german) +33 1 69 35 48 48 (french) www.freescale.com/support japan: freescale semiconductor japan ltd. headquarters arco tower 15f 1-8-1, shimo-meguro, meguro-ku, tokyo 153-0064 japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com asia/pacific: freescale semiconductor china ltd. exchange building 23f no. 118 jianguo road chaoyang district beijing 100022 china +86 10 5879 8000 support.asia@freescale.com freescale semiconductor literature distribution center p.o. box 5405 denver, colorado 80217 1-800-441-2447 or +1-303-675-2140 fax: +1-303-675-2150 ldcforfreescalesemiconduc tor@hibbertgroup.com information in this document is provid ed solely to enable system and software implementers to use freescale semiconduc tor products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. freescale semiconductor reserves the right to make changes without further notice to any products herein. freescale semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does freescale semiconductor assume any liability arising out of the application or use of any product or circuit, and specif ically disclaims any and all liability, including without limitation consequential or incidental damages. ?typical? parameters that may be provided in freescale semiconductor data s heets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals?, must be validated for each customer application by customer?s technical experts. freescale semiconductor does not convey any license under its patent rights nor the rights of others. freescale semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applic ations intended to support or sustain life, or for any other application in which the failure of the freescale semiconductor product could create a situation where personal injury or death may occur. should buyer purchase or use freescale semiconductor products for any such unintended or unauthorized application, buyer shall indemnify and hold freescale semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that freescale semiconductor was negligent regarding the design or manufacture of the part. rohs-compliant and/or pb-free versions of freescale products have the functionality and electrical characteristics as thei r non-rohs-compliant and/or non-pb-free counterparts. for further information, see http://www.freescale.com or contact your freescale sales representative. for information on freescale?s environmental products program, go to http://www.freescale.com/epp . freescale? and the freescale logo are trademarks of freescale semiconductor, inc. all other product or service names are the property of their respective owners. ? freescale semiconductor, inc. 2009. all rights reserved. preliminary?subject to change without notice |
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